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<title>Microprocessor chronology</title>

</head>

Microprocessor chronology

</h1>

</header>

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</style><div role="note" class="hatnote navigation-not-searchable">See also: <a href="Microprocessor#History" title="Microprocessor">Microprocessor § History</a></div>

The first chips that could be considered <a href="Microprocessors" class="mw-redirect" title="Microprocessors">microprocessors</a> were designed and manufactured in the late 1960s and early 1970s, including the MP944 used in the <a href="F-14_CADC" title="F-14 CADC">Grumman F-14 <abbr title="Central Air Data Computer">CADC</abbr></a>.<a href="#cite_note-1">[1]</a> Intel's 4004 of 1971 is widely regarded as the first commercial microprocessor.<a href="#cite_note-2">[2]</a>

Designers predominantly used <a href="MOSFET" title="MOSFET">MOSFET</a> transistors with <a href="PMOS_logic" title="PMOS logic">pMOS logic</a> in the early 1970s, switching to <a href="NMOS_logic" title="NMOS logic">nMOS logic</a> after the mid-1970s. nMOS had the advantage that it could run on a single voltage, typically +5V, which simplified the power supply requirements and allowed it to be easily interfaced with the wide variety of +5V <a href="Transistor-transistor_logic" class="mw-redirect" title="Transistor-transistor logic">transistor-transistor logic</a> (TTL) devices. nMOS had the disadvantage that it was more susceptible to electronic noise generated by slight impurities in the underlying silicon material, and it was not until the mid-1970s that these, sodium in particular, were successfully removed to the required levels. At that time, around 1975, nMOS quickly took over the market.<a href="#cite_note-3">[3]</a>

This corresponded with the introduction of new <a href="Photomask" title="Photomask">semiconductor masking</a> systems, notably the <a href="Micralign" title="Micralign">Micralign</a> system from <a href="Perkin-Elmer" class="mw-redirect" title="Perkin-Elmer">Perkin-Elmer</a>. Micralign projected an image of the mask onto the silicon wafer, never touching it directly, which eliminated the previous problems when the mask would be lifted off the surface and take away some of the <a href="Photoresist" title="Photoresist">photoresist</a> along with it, ruining the chips on that portion of the wafer.<a href="#cite_note-4">[4]</a> By reducing the number of flawed chips, from about 70% to 10%, the cost of complex designs like early microprocessors fell by the same amount. Systems based on contact aligners cost on the order of $300 in single-unit quantities, the <a href="MOS_6502" class="mw-redirect" title="MOS 6502">MOS 6502</a>, designed specifically to take advantage of these improvements, cost only $25.<a href="#cite_note-5">[5]</a>

This period also saw considerable experimentation with various <a href="Word_length" class="mw-redirect" title="Word length">word lengths</a>. Early on, <a href="4-bit_computing" title="4-bit computing">4-bit</a> processors were common, like the Intel 4004, simply because making a wider word length could not be accomplished cost-effectively in the room available on the small wafers of the era, especially when the majority would be defective. As yields improved, wafer sizes grew, and feature size continued to be reduced, more complex <a href="8-bit_computing" title="8-bit computing">8-bit</a> designs emerged like the <a href="Intel_8080" title="Intel 8080">Intel 8080</a> and 6502. <a href="16-bit_computing" title="16-bit computing">16-bit</a> processors emerged early but were expensive; by the decade's end, low-cost 16-bit designs like the <a href="Zilog_Z8000" title="Zilog Z8000">Zilog Z8000</a> were becoming common. Some unusual word lengths were also produced, including <a href="12-bit_computing" title="12-bit computing">12-bit</a> and 20-<a href="Bit" title="Bit">bit</a>, often matching a design that had previously been implemented in a multi-chip format in a <a href="Minicomputer" title="Minicomputer">minicomputer</a>. These had largely disappeared by the end of the decade as minicomputers moved to <a href="32-bit_computing" title="32-bit computing">32-bit</a> formats.

<th>Date

</th>

<th>Name

</th>

<th>Developer

</th>

<th data-sort-type="number"><a href="Clock_rate" title="Clock rate">Max clock</a> (first version)

</th>

<th data-sort-type="number"><a href="Word_size" class="mw-redirect" title="Word size">Word size</a> (<a href="Bit" title="Bit">bits</a>)

</th>

<th data-sort-type="number"><a href="Semiconductor_fabrication_process" class="mw-redirect" title="Semiconductor fabrication process">Process</a>

</th>

<th data-sort-type="number"><a href="Integrated_circuit" title="Integrated circuit">Chips</a><a href="#cite_note-Belzer-6">[6]</a>

</th>

<th data-sort-type="number"><a href="Transistor_count" title="Transistor count">Transistors</a>

</th>

<th><a href="MOSFET" title="MOSFET">MOSFET</a>

</th>

</th></tr>

<tr>

<td>1970

</td>

</td>

<td>Four-Phase Systems

</td>

<td>1 MHz

</td>

<td>8-<a href="Bit_slicing" title="Bit slicing">bit slice</a><a href="#cite_note-7">[a]</a>

</td>

</td>

</td>

<td>4,000

</td>

<td>MOS

</td>

</td></tr>

<tr>

<td>1970

</td>

</td>

<td>Texas Instruments

</td>

<td>400 kHz

</td>

</td>

</td>

<td>1

</td>

<td>~5,000

</td>

</td>

</td></tr>

<tr>

<td>1971

</td>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>740 kHz

</td>

</td>

</td>

<td>1

</td>

<td>2,250

</td>

</td>

</td></tr>

<tr>

<td>1972

</td>

<td>PPS-25

</td>

<td><a href="Fairchild_Semiconductor" title="Fairchild Semiconductor">Fairchild</a>

</td>

<td>400 kHz

</td>

<td>4

</td>

<td>

</td>

<td>2

</td>

<td>

</td>

<td>pMOS

</td>

</td></tr>

<tr>

<td>1972

</td>

<td>μPD700

</td>

</td>

<td>

</td>

<td>4

</td>

<td>

</td>

<td>1

</td>

<td>

</td>

<td>

</td>

</td></tr>

<tr>

<td>1972

</td>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>500 kHz

</td>

</td>

<td>10 μm

</td>

<td>1

</td>

<td>3,500

</td>

<td>pMOS

</td>

<td>

</td></tr>

<tr>

<td>1972

</td>

<td>PPS-4

</td>

<td><a href="Rockwell_International" title="Rockwell International">Rockwell</a>

</td>

<td>200 kHz

</td>

<td>4

</td>

<td>

</td>

<td>1

</td>

<td>

</td>

<td>pMOS

</td>

</td></tr>

<tr>

<td>1973

</td>

</td>

<td><a href="National_Semiconductor" title="National Semiconductor">National</a>

</td>

<td>715 kHz

</td>

</td>

<td>

</td>

<td>5

</td>

<td>

</td>

<td>pMOS

</td>

</td></tr>

<tr>

<td>1973

</td>

</td>

</td>

<td>2 MHz

</td>

<td>4

</td>

</td>

<td>1

</td>

<td>2,500

</td>

</td>

</td></tr>

<tr>

<td>1973

</td>

</td>

<td><a href="Toshiba" title="Toshiba">Toshiba</a>

</td>

<td>1 MHz

</td>

</td>

</td>

<td>1

</td>

<td>2,800 <a href="Silicon_gate" class="mw-redirect" title="Silicon gate">silicon gates</a>

</td>

<td>pMOS

</td>

</td></tr>

<tr>

<td>1973

</td>

<td>Mini-D

</td>

<td><a href="Burroughs_Corporation" title="Burroughs Corporation">Burroughs</a>

</td>

<td>1 MHz

</td>

<td>8

</td>

<td>

</td>

<td>1

</td>

<td>

</td>

<td>pMOS

</td>

</td></tr>

<tr>

<td>1974

</td>

<td>IMP-8

</td>

<td><a href="National_Semiconductor" title="National Semiconductor">National</a>

</td>

<td>715 kHz

</td>

<td>8

</td>

<td>

</td>

<td>3

</td>

<td>

</td>

<td>pMOS

</td>

</td></tr>

<tr>

<td>1974

</td>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>2 MHz

</td>

<td>8

</td>

<td>6 μm

</td>

<td>1

</td>

<td>6,000

</td>

<td>NMOS

</td>

<td>

</td></tr>

<tr>

<td>1974

</td>

</td>

</td>

<td>2 MHz

</td>

<td>8

</td>

<td>

</td>

<td>1

</td>

<td>

</td>

<td>NMOS

</td>

</td></tr>

<tr>

<td>1974

</td>

</td>

<td><a href="Mostek" title="Mostek">Mostek</a>

</td>

<td>1.4 MHz

</td>

<td>8

</td>

<td>

</td>

<td>1

</td>

<td>

</td>

<td>pMOS

</td>

</td></tr>

<tr>

<td>1974

</td>

</td>

</td>

<td>2 MHz

</td>

</td>

<td>

</td>

<td>2

</td>

<td>

</td>

<td>NMOS

</td>

</td></tr>

<tr>

<td>1974

</td>

<td>IMP-4

</td>

<td><a href="National_Semiconductor" title="National Semiconductor">National</a>

</td>

<td>500 kHz

</td>

<td>4

</td>

<td>

</td>

<td>3

</td>

<td>

</td>

<td>pMOS

</td>

</td></tr>

<tr>

<td>1974

</td>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>740 kHz

</td>

<td>4

</td>

<td>10 μm

</td>

<td>1

</td>

<td>3,000

</td>

<td>pMOS

</td>

<td>

</td></tr>

<tr>

<td>1974

</td>

</td>

<td><a href="Motorola" title="Motorola">Motorola</a>

</td>

<td>1 MHz

</td>

<td>8

</td>

<td>-

</td>

<td>1

</td>

<td>4,100

</td>

<td>NMOS

</td>

</td></tr>

<tr>

<td>1974

</td>

</td>

<td><a href="Texas_Instruments" title="Texas Instruments">Texas Instruments</a>

</td>

<td>400 kHz

</td>

<td>4

</td>

<td>8 μm

</td>

<td>1

</td>

<td>8,000

</td>

<td>pMOS,nMOS,cMOS

</td>

<td>

</td></tr>

<tr>

<td>1974

</td>

</td>

<td><a href="National_Semiconductor" title="National Semiconductor">National</a>

</td>

<td>1.33 MHz

</td>

<td>16

</td>

<td>

</td>

<td>1

</td>

<td>

</td>

<td>pMOS

</td>

</td></tr>

<tr>

<td>1974

</td>

</td>

<td><a href="National_Semiconductor" title="National Semiconductor">National</a>

</td>

<td>1 MHz

</td>

<td>8

</td>

<td>

</td>

<td>1

</td>

<td>

</td>

<td>pMOS

</td>

<td>

</td></tr>

<tr>

<td>1975

</td>

</td>

<td><a href="Intersil" title="Intersil">Intersil</a>

</td>

<td>4 MHz

</td>

<td>12

</td>

<td>-

</td>

<td>1

</td>

<td>4,000

</td>

</td>

</td></tr>

<tr>

<td>1975

</td>

<td>TLCS-12A

</td>

<td><a href="Toshiba" title="Toshiba">Toshiba</a>

</td>

<td>1.2 MHz

</td>

<td>12

</td>

<td>-

</td>

<td>1

</td>

<td>

</td>

<td>pMOS

</td>

</td></tr>

<tr>

<td>1975

</td>

</td>

<td><a href="Signetics" title="Signetics">Signetics</a>

</td>

<td>1.2 MHz

</td>

<td>8

</td>

<td>

</td>

<td>1

</td>

<td>

</td>

<td>NMOS

</td>

</td></tr>

<tr>

<td>1975

</td>

<td>PPS-8

</td>

<td><a href="Rockwell_International" title="Rockwell International">Rockwell</a>

</td>

<td>256 kHz

</td>

<td>8

</td>

<td>

</td>

<td>1

</td>

<td>

</td>

<td>pMOS

</td>

</td></tr>

<tr>

<td>1975

</td>

</td>

<td><a href="Fairchild_Semiconductor" title="Fairchild Semiconductor">Fairchild</a>

</td>

<td>2 MHz

</td>

<td>8

</td>

<td>

</td>

<td>1

</td>

<td>

</td>

<td>NMOS

</td>

</td></tr>

<tr>

<td>1975

</td>

</td>

</td>

<td>2 MHz

</td>

<td>8

</td>

<td>5 μm

</td>

<td>2

</td>

<td>5,000

</td>

<td>CMOS

</td>

</td></tr>

<tr>

<td>1975

</td>

</td>

<td><a href="MOS_Technology" title="MOS Technology">MOS Technology</a>

</td>

<td>1 MHz

</td>

<td>8

</td>

<td>-

</td>

<td>1

</td>

<td>3,510

</td>

<td>NMOS (<a href="Dynamic_logic_(digital_electronics)" title="Dynamic logic (digital electronics)">dynamic</a>)

</td>

<td>

</td></tr>

<tr>

<td>1975

</td>

<td>PFL-16A (MN 1610)

</td>

<td><a href="Panafacom" title="Panafacom">Panafacom</a>

</td>

<td>2 MHz

</td>

<td>16

</td>

<td>-

</td>

<td>1

</td>

<td>

</td>

<td>NMOS

</td>

</td></tr>

<tr>

<td>1975

</td>

<td>BPC

</td>

<td><a href="Hewlett_Packard" class="mw-redirect" title="Hewlett Packard">Hewlett Packard</a>

</td>

<td>10 MHz

</td>

<td>16

</td>

<td>-

</td>

<td>1

</td>

<td>6,000 (+ <a href="Read-only_memory" title="Read-only memory">ROM</a>)

</td>

<td>NMOS

</td>

</td></tr>

<tr>

<td>1975

</td>

</td>

<td><a href="Western_Digital" title="Western Digital">Western Digital</a>

</td>

<td>3.3 MHz

</td>

</td>

<td>-

</td>

</td>

<td>

</td>

<td>NMOS

</td>

</td></tr>

<tr>

<td>1975

</td>

</td>

<td><a href="General_Instrument" title="General Instrument">General Instrument</a>

</td>

<td>3.3 MHz

</td>

<td>16

</td>

<td>

</td>

<td>1

</td>

<td>

</td>

<td>NMOS

</td>

</td></tr>

<tr>

<td>1976

</td>

</td>

</td>

<td>6.4 MHz

</td>

<td>8

</td>

<td>

</td>

<td>1

</td>

<td>

</td>

<td>CMOS

</td>

</td></tr>

<tr>

<td>1976

</td>

</td>

<td><a href="Zilog" title="Zilog">Zilog</a>

</td>

<td>2.5 MHz

</td>

<td>8

</td>

<td>4 μm

</td>

<td>1

</td>

<td>8,500

</td>

<td>NMOS

</td>

<td>

</td></tr>

<tr>

<td>1976

</td>

</td>

<td><a href="Texas_Instruments" title="Texas Instruments">Texas Instruments</a>

</td>

<td>3.3 MHz

</td>

<td>16

</td>

<td>-

</td>

<td>1

</td>

<td>8,000

</td>

<td>nMOS

</td>

<td>

</td></tr>

<tr>

<td>1976

</td>

</td>

<td><a href="Signetics" title="Signetics">Signetics</a>

</td>

<td>8 MHz

</td>

<td>8

</td>

<td>

</td>

<td>1

</td>

<td>

</td>

<td><a href="Bipolar_junction_transistor" title="Bipolar junction transistor">Bipolar</a>

</td>

</td></tr>

<tr>

<td>1977

</td>

<td><a href="BELLMAC-8" title="BELLMAC-8">Bellmac-8</a> (WE212)

</td>

</td>

<td>2.0 MHz

</td>

<td>8

</td>

<td>5 μm

</td>

<td>1

</td>

<td>7,000

</td>

<td>CMOS

</td>

<td>

</td></tr>

<tr>

<td>1977

</td>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>3.0 MHz

</td>

<td>8

</td>

</td>

<td>1

</td>

<td>6,500

</td>

<td>nMOS

</td>

<td>

</td></tr>

<tr>

<td>1977

</td>

</td>

<td><a href="Motorola" title="Motorola">Motorola</a>

</td>

<td>1.0 MHz

</td>

</td>

<td>

</td>

<td>1

</td>

<td>

</td>

<td>CMOS

</td>

<td>

</td></tr>

<tr>

<td>1978

</td>

</td>

<td><a href="Motorola" title="Motorola">Motorola</a>

</td>

<td>1 MHz

</td>

<td>8

</td>

<td>5 μm

</td>

<td>1

</td>

<td>9,000

</td>

<td>NMOS

</td>

<td>

</td></tr>

<tr>

<td>1978

</td>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>5 MHz

</td>

<td>16

</td>

<td>3 μm

</td>

<td>1

</td>

<td>29,000

</td>

<td>nMOS

</td>

<td>

</td></tr>

<tr>

<td>1978

</td>

</td>

<td><a href="Motorola" title="Motorola">Motorola</a>

</td>

<td>-

</td>

<td>8

</td>

<td>5 μm

</td>

<td>1

</td>

<td>35,000

</td>

<td>nMOS

</td>

<td>

</td></tr>

<tr>

<td>1979

</td>

</td>

<td><a href="Zilog" title="Zilog">Zilog</a>

</td>

<td>-

</td>

<td>16

</td>

<td>-

</td>

<td>1

</td>

<td>17,500

</td>

<td>nMOS

</td>

<td>

</td></tr>

<tr>

<td>1979

</td>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>5 MHz

</td>

</td>

<td>3 μm

</td>

<td>1

</td>

<td>29,000

</td>

<td>NMOS (<a href="HMOS" class="mw-redirect" title="HMOS">HMOS</a>)

</td>

<td>

</td></tr>

<tr>

<td>1979

</td>

</td>

<td><a href="Motorola" title="Motorola">Motorola</a>

</td>

<td>8 MHz

</td>

</td>

<td>3.5 μm

</td>

<td>1

</td>

<td>68,000

</td>

<td>NMOS (HMOS)

</td>

</td></tr></tbody></table>

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</style><div class="reflist reflist-lower-alpha">

<li id="cite_note-7"><a href="#cite_ref-7">^</a> The AL1 chip is an 8-bit slice <a href="Arithmetic_logic_unit" title="Arithmetic logic unit">arithmetic logic unit</a> with registers. Four-Phase did not sell the AL1 individually but as part of a system combining three of these 8-bit AL1 chips to yield a multi-chip CPU with a 24-bit word size.

</li>

<li id="cite_note-10"><a href="#cite_ref-10">^</a> A 1995 court demo combined one AL1 with ROM, RAM, and I/0 to argue that the AL1 alone be considered a microprocessor.<a href="#cite_note-8">[7]</a> But because it requires an external <a href="Microcode" title="Microcode">microcode</a> controller, another view disagrees.<a href="#cite_note-9">[8]</a>

</li>

<li id="cite_note-13"><a href="#cite_ref-13">^</a> TMS1802NC is the original designation of the TMS0102, which is considered a <a href="Microcontroller" title="Microcontroller">microcontroller</a> because it incorporates all program ROM internally. It can't execute external code and programming is done during manufacture. The term <a href="Microprocessor" title="Microprocessor">microprocessor</a> may instead be reserved for devices that can execute external code.

</li>

<li id="cite_note-19"><a href="#cite_ref-19">^</a> According to <a href="#CITEREFOgdin1975">Ogdin 1975</a>, the Fairchild PPS-25 was first delivered in 2Q 1971 and the Intel 4004 in 4Q 1971.

</li>

<li id="cite_note-23"><a href="#cite_ref-23">^</a> The 16-bit registers and ALU were implemented by combining four identical 4-<a href="Bit_slice" class="mw-redirect" title="Bit slice">bit slice</a> chips. The <a href="National_Semiconductor_PACE" title="National Semiconductor PACE">National Semiconductor PACE</a> reimplemented its architecture as the first single-chip 16-bit microprocessor.

</li>

<li id="cite_note-40"><a href="#cite_ref-40">^</a> Internally is an 8-bit processor, but is <a href="Microcode" title="Microcode">micro-programmed</a> to emulate a 16-bit CPU.

</li>

<li id="cite_note-41"><a href="#cite_ref-41">^</a> Later microprocessors reused this <a href="Chipset" title="Chipset">chipset</a>, for instance the <a href="LSI-11" class="mw-redirect" title="LSI-11">LSI-11</a> in 1975 used 4 chips and the <a href="WD16" title="WD16">WD16</a> in 1976 used 5 chips.

</li>

<li id="cite_note-49"><a href="#cite_ref-49">^</a> The Intel 8088 had an <a href="8-bit_computing" title="8-bit computing">8-bit</a> external data bus, but internally used a <a href="16-bit_computing" title="16-bit computing">16-bit</a> architecture.

</li>

<li id="cite_note-50"><a href="#cite_ref-50">^</a> The Motorola 68000 had a 16-bit external data bus, but internally used <a href="32-bit_computing" title="32-bit computing">32-bit</a> registers.

</li>

</ol></div></div>

As <a href="Moore's_Law" class="mw-redirect" title="Moore's Law">Moore's Law</a> continued to drive the industry towards more complex chip designs, the expected widespread move from 8-bit designs of the 1970s to 16-bit designs almost didn't occur; instead, new <a href="32-bit_computing" title="32-bit computing">32-bit</a> designs like the <a href="Motorola_68000" title="Motorola 68000">Motorola 68000</a> and <a href="National_Semiconductor_NS32000" class="mw-redirect" title="National Semiconductor NS32000">National Semiconductor NS32000</a> emerged that offered far more performance. The only widespread use of 16-bit systems was in the <a href="IBM_PC" class="mw-redirect" title="IBM PC">IBM PC</a>, which had selected the <a href="Intel_8088" title="Intel 8088">Intel 8088</a> in 1979 before the new designs had matured.

Another change was the move to <a href="CMOS" title="CMOS">CMOS</a> gates as the primary method of building complex CPUs. CMOS had been available since the early 1970s; <a href="RCA" title="RCA">RCA</a> introduced the <a href="RCA_1802" title="RCA 1802">COSMAC</a> processor using CMOS in 1975.<a href="#cite_note-52">[43]</a> Whereas earlier systems used a single <a href="Transistor" title="Transistor">transistor</a> as the basis for each "gate", CMOS used a two-sided design, essentially making it twice as expensive to build. Its advantage was that its logic was not based on the voltage of a transistor compared to the silicon substrate, but the difference in voltages between the two sides, which was detectable at much lower power levels. As processor complexity continued to grow, power dissipation had become a significant concern and chips were prone to overheating; CMOS greatly reduced this problem and quickly took over the market.<a href="#cite_note-Kuhn-53">[44]</a> This was aided by the uptake of CMOS by Japanese firms while US firms remained on nMOS, giving the Japanese industry a major advance during the 1980s.<a href="#cite_note-54">[45]</a>

Semiconductor fabrication techniques continued to improve throughout. The Micralign, which had "created the modern IC industry", was obsolete by the early 1980s. They were replaced by the new <a href="Stepper" title="Stepper">steppers</a>, which used high magnifications and extremely powerful light sources to allow a large mask to be copied onto the wafer at ever-smaller sizes. This technology allowed the industry to break below the former 1 micron limit.

Key <a href="Home_computer" title="Home computer">home computers</a> in the early part of the decade predominantly use processors developed in the 1970s. Versions of the 6502, first released in 1975, powered the <a href="Commodore_64" title="Commodore 64">Commodore 64</a>, <a href="Apple_II" title="Apple II">Apple II</a>, <a href="BBC_Micro" title="BBC Micro">BBC Micro</a>, and <a href="Atari_8-bit_computers" title="Atari 8-bit computers">Atari 8-bit computers</a>. The 8-bit <a href="Zilog_Z80" title="Zilog Z80">Zilog Z80</a> (1976) is at the core of the <a href="ZX_Spectrum" title="ZX Spectrum">ZX Spectrum</a>, <a href="MSX" title="MSX">MSX</a> systems and many others. The 8086-based IBM PC, launched in 1981, started the move to 16-bit, but was soon passed by the 68000-based 16/32-bit <a href="Macintosh" class="mw-redirect" title="Macintosh">Macintosh</a>, then the <a href="Atari_ST" title="Atari ST">Atari ST</a> and <a href="Amiga" title="Amiga">Amiga</a>. IBM PC compatibles moved to 32-bit with the introduction of the <a href="Intel_80386" class="mw-redirect" title="Intel 80386">Intel 80386</a> in late 1985, although 386-based systems were considerably expensive at the time.

In addition to ever-growing word lengths, microprocessors began to add additional functional units that had previously been optional external parts. By the middle of the decade, <a href="Memory_management_unit" title="Memory management unit">memory management units</a> (MMUs) were becoming commonplace, first appearing on designs like the <a href="Intel_80286" title="Intel 80286">Intel 80286</a> and <a href="Motorola_68030" title="Motorola 68030">Motorola 68030</a>. By the end of the decade, <a href="Floating_point_unit" class="mw-redirect" title="Floating point unit">floating point units</a> (FPUs) were being added, first appearing on 1989s <a href="I486" title="I486">Intel 486</a> and followed the next year by the <a href="Motorola_68040" title="Motorola 68040">Motorola 68040</a>.

Another change that began during the 1980s involved overall design philosophy with the emergence of the <a href="Reduced_instruction_set_computer" title="Reduced instruction set computer">reduced instruction set computer</a>, or RISC. Although the concept was first developed by IBM in the 1970s, the company did not introduce powerful systems based on it, largely for fear of cannibalizing their sales of larger <a href="Mainframe" class="mw-redirect" title="Mainframe">mainframe</a> systems. Market introduction was driven by smaller companies like <a href="MIPS_Technologies" title="MIPS Technologies">MIPS Technologies</a>, <a href="SPARC" title="SPARC">SPARC</a> and <a href="Arm_Ltd." class="mw-redirect" title="Arm Ltd.">ARM</a>. These companies did not have access to high-end fabrication like Intel and Motorola, but were able to introduce chips that were highly competitive with those companies with a fraction of the complexity. By the end of the decade, every major vendor was introducing a RISC design of their own, like the <a href="IBM_Power_microprocessors" title="IBM Power microprocessors">IBM POWER</a>, <a href="Intel_i860" title="Intel i860">Intel i860</a> and <a href="Motorola_88000" title="Motorola 88000">Motorola 88000</a>.

<th>Date

</th>

<th>Name

</th>

<th>Developer

</th>

<th data-sort-type="number">Max Clock (first version)

</th>

<th data-sort-type="number">Word size (bits)

</th>

<th data-sort-type="number">Process

</th>

<th data-sort-type="number">Transistors

</th></tr>

<tr>

<td>1980

</td>

</td>

<td><a href="National_Semiconductor" title="National Semiconductor">National Semiconductor</a>

</td>

<td>-

</td>

<td>16/32

</td>

<td>-

</td>

<td>60,000

</td></tr>

<tr>

<td>1980

</td>

<td>BELLMAC-32/WE 32000

</td>

</td>

<td>

</td>

<td>32

</td>

<td>

</td>

<td>150,000

</td></tr>

<tr>

<td>1981

</td>

<td>6120

</td>

<td><a href="Harris_Corporation" title="Harris Corporation">Harris Corporation</a>

</td>

<td>10 MHz

</td>

<td>12

</td>

<td>-

</td>

</td></tr>

<tr>

<td>1981

</td>

</td>

</td>

<td>10 MHz

</td>

</td>

<td>2 μm

</td>

<td>45,000

</td></tr>

<tr>

<td>1981

</td>

</td>

</td>

<td>2.5 MHz

</td>

<td>16

</td>

<td>5 μm

</td>

<td>17,000 (<a href="NMOS_logic" title="NMOS logic">NMOS</a>)

</td></tr>

<tr>

<td>1982

</td>

</td>

<td><a href="University_of_California%2C_Berkeley" title="University of California, Berkeley">UC Berkeley</a>

</td>

<td>1 MHz

</td>

<td>-

</td>

<td>5 μm

</td>

<td>44,420 (<a href="NMOS_logic" title="NMOS logic">NMOS</a>)

</td></tr>

<tr>

<td>1982

</td>

<td><a href="FOCUS_(hardware)" class="mw-redirect" title="FOCUS (hardware)">FOCUS</a>

</td>

<td><a href="Hewlett_Packard" class="mw-redirect" title="Hewlett Packard">Hewlett Packard</a>

</td>

<td>18 MHz

</td>

<td>32

</td>

</td>

<td>450,000

</td></tr>

<tr>

<td>1982

</td>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>6 MHz

</td>

<td>16

</td>

<td>-

</td>

<td>55,000

</td></tr>

<tr>

<td>1982

</td>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>8 MHz

</td>

<td>8/16

</td>

<td>-

</td>

<td>55,000

</td></tr>

<tr>

<td>1982

</td>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>6 MHz

</td>

<td>16

</td>

<td>1.5 μm

</td>

<td>134,000

</td></tr>

<tr>

<td>1983

</td>

</td>

<td><a href="University_of_California%2C_Berkeley" title="University of California, Berkeley">UC Berkeley</a>

</td>

<td>3 MHz

</td>

<td>-

</td>

<td>3 μm

</td>

<td>40,760 (<a href="NMOS_logic" title="NMOS logic">NMOS</a>)

</td></tr>

<tr>

<td>1983

</td>

</td>

<td><a href="Stanford_University" title="Stanford University">Stanford University</a>

</td>

<td>2 MHz

</td>

<td>32

</td>

<td>3 μm

</td>

<td>25,000

</td></tr>

<tr>

<td>1983

</td>

</td>

<td><a href="Western_Design_Center" title="Western Design Center">Western Design Center</a>

</td>

<td>-

</td>

<td>16

</td>

<td>-

</td>

<td>-

</td></tr>

<tr>

<td>1984

</td>

</td>

<td><a href="Motorola" title="Motorola">Motorola</a>

</td>

<td>16 MHz

</td>

<td>32

</td>

<td>2 μm

</td>

<td>190,000

</td></tr>

<tr>

<td>1984

</td>

</td>

<td><a href="National_Semiconductor" title="National Semiconductor">National Semiconductor</a>

</td>

<td>-

</td>

<td>32

</td>

<td>-

</td>

<td>70,000

</td></tr>

<tr>

<td>1984

</td>

</td>

</td>

<td>5 MHz

</td>

<td>8/16

</td>

<td>-

</td>

<td>63,000

</td></tr>

<tr>

<td>1985

</td>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>12 MHz

</td>

<td>32

</td>

<td>1.5 μm

</td>

<td>275,000

</td></tr>

<tr>

<td>1985

</td>

<td><a href="MicroVAX_78032" title="MicroVAX 78032">MicroVax II 78032</a>

</td>

</td>

<td>5 MHz

</td>

<td>32

</td>

<td>3.0 μm

</td>

<td>125,000

</td></tr>

<tr>

<td>1985

</td>

</td>

</td>

<td>8 MHz

</td>

<td>32

</td>

<td>2 μm

</td>

<td>115,000

</td></tr>

<tr>

</td>

<td>Novix NC4016

</td>

<td><a href="Harris_Corporation" title="Harris Corporation">Harris Corporation</a>

</td>

<td>8 MHz

</td>

<td>16

</td>

</td>

</td></tr>

<tr>

<td>1986

</td>

</td>

<td><a href="Zilog" title="Zilog">Zilog</a>

</td>

<td>-

</td>

<td>32

</td>

<td>-

</td>

<td>91,000

</td></tr>

<tr>

<td>1986

</td>

<td><a href="MB86900" title="MB86900">SPARC MB86900</a>

</td>

<td><a href="Fujitsu" title="Fujitsu">Fujitsu</a><a href="#cite_note-cpushack-61">[52]</a><a href="#cite_note-cpu-collection-62">[53]</a><a href="#cite_note-timeline-63">[54]</a>

</td>

<td>15 MHz

</td>

<td>32

</td>

</td>

<td>800,000

</td></tr>

<tr>

<td>1986

</td>

</td>

</td>

<td>16 MHz

</td>

<td>16/32

</td>

<td>1.5 μm

</td>

<td>375,000

</td></tr>

<tr>

<td>1987

</td>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>10 MHz

</td>

<td>16

</td>

<td>-

</td>

<td>56,000 (<a href="CMOS" title="CMOS">CMOS</a>)

</td></tr>

<tr>

<td>1987

</td>

</td>

</td>

<td>12.5 MHz

</td>

<td>32

</td>

<td>2.0 μm

</td>

<td>134,000

</td></tr>

<tr>

<td>1987

</td>

</td>

<td><a href="Acorn_Computers" title="Acorn Computers">Acorn</a>

</td>

<td>8 MHz

</td>

<td>32

</td>

<td>2 μm

</td>

</td></tr>

<tr>

<td>1987

</td>

<td><a href="TRON_Project" class="mw-redirect" title="TRON Project">Gmicro/200</a><a href="#cite_note-66">[57]</a>

</td>

<td><a href="Hitachi" title="Hitachi">Hitachi</a>

</td>

<td>-

</td>

<td>-

</td>

</td>

<td>730,000

</td></tr>

<tr>

<td>1987

</td>

</td>

<td><a href="Motorola" title="Motorola">Motorola</a>

</td>

<td>16 MHz

</td>

<td>32

</td>

<td>1.3 μm

</td>

<td>273,000

</td></tr>

<tr>

<td>1987

</td>

</td>

</td>

<td>20 MHz

</td>

<td>16/32

</td>

<td>1.5 μm

</td>

<td>385,000

</td></tr>

<tr>

<td>1988

</td>

</td>

</td>

<td>25 MHz

</td>

<td>32

</td>

<td>1.2 μm

</td>

<td>120,000

</td></tr>

<tr>

<td>1988

</td>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>12 MHz

</td>

<td>16/32

</td>

<td>-

</td>

<td>-

</td></tr>

<tr>

<td>1988

</td>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>10 MHz

</td>

<td>33/32

</td>

<td>1.5 μm

</td>

<td>250,000

</td></tr>

<tr>

<td>1989

</td>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>16–33 MHz

</td>

<td>33/32

</td>

<td>0.8 μm

</td>

<td>600,000

</td></tr>

<tr>

<td>1989

</td>

<td><a href="Rigel_(microprocessor)" title="Rigel (microprocessor)">VAX DC520 "Rigel"</a>

</td>

</td>

<td>35 MHz

</td>

<td>32

</td>

<td>1.5 μm

</td>

<td>320,000

</td></tr>

<tr>

<td>1989

</td>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>25 MHz

</td>

<td>32

</td>

<td>1 μm

</td>

<td>1,180,000

</td></tr>

<tr>

<td>1989

</td>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>25 MHz

</td>

<td>32

</td>

<td>1 μm

</td>

<td>1,000,000

</td></tr></tbody></table>

The <a href="32-bit_computing" title="32-bit computing">32-bit</a> microprocessor dominated the consumer market in the 1990s. Processor clock speeds increased by more than tenfold between 1990 and 1999, and <a href="64-bit_computing" title="64-bit computing">64-bit</a> processors began to emerge later in the decade. In the 1990s, microprocessors no longer used the same clock speed for the processor and the <a href="Random-access_memory" title="Random-access memory">RAM</a>. Processors began to have a <a href="Front-side_bus" title="Front-side bus">front-side bus</a> (FSB) clock speed used in communication with RAM and other components. Typically, the processor itself ran at a clock speed that was a multiple of the FSB clock speed. Intel's Pentium III, for example, had an internal clock speed of 450–600 MHz and an FSB speed of 100–133 MHz. Only the processor's internal clock speed is shown here.

<th>Date

</th>

<th>Name

</th>

<th>Developer

</th>

<th data-sort-type="number">Clock

</th>

<th data-sort-type="number">Word size (bits)

</th>

<th data-sort-type="number">Process

</th>

<th data-sort-type="number">Transistors (millions)

</th>

<th data-sort-type="number"><a href="Multithreading_(computer_hardware)" class="mw-redirect" title="Multithreading (computer hardware)">Threads</a>

</th></tr>

<tr>

<td>1990

</td>

</td>

<td><a href="Motorola" title="Motorola">Motorola</a>

</td>

<td>40 MHz

</td>

<td>32

</td>

<td>-

</td>

<td>1.2

</td>

<td>

</td></tr>

<tr>

<td>1990

</td>

<td><a href="POWER1" title="POWER1">POWER1</a>

</td>

</td>

<td>20–30 MHz

</td>

<td>32

</td>

</td>

<td>6.9

</td>

<td>

</td></tr>

<tr>

<td>1991

</td>

</td>

<td><a href="MIPS_Computer_Systems" class="mw-redirect" title="MIPS Computer Systems">MIPS Computer Systems</a>

</td>

<td>100 MHz

</td>

</td>

</td>

<td>1.35

</td>

<td>

</td></tr>

<tr>

<td>1991

</td>

</td>

</td>

<td>62.5–90.91 MHz

</td>

<td>32

</td>

</td>

<td>1.3

</td>

<td>

</td></tr>

<tr>

<td>1991

</td>

</td>

</td>

<td>33 MHz

</td>

<td>32

</td>

<td>800 nm

</td>

</td>

<td>

</td></tr>

<tr>

<td>1992

</td>

</td>

<td><a href="Hitachi" title="Hitachi">Hitachi</a>

</td>

</td>

<td>32

</td>

<td>800 nm

</td>

</td>

<td>

</td></tr>

<tr>

<td>1992

</td>

<td><a href="Alpha_21064" title="Alpha 21064">Alpha 21064</a>

</td>

</td>

<td>100–200 MHz

</td>

<td>64

</td>

<td>750 nm

</td>

<td>1.68

</td>

<td>

</td></tr>

<tr>

<td>1992

</td>

<td><a href="MicroSPARC_I" class="mw-redirect" title="MicroSPARC I">microSPARC I</a>

</td>

</td>

<td>40–50 MHz

</td>

<td>32

</td>

<td>800 nm

</td>

<td>0.8

</td>

<td>

</td></tr>

<tr>

<td>1992

</td>

</td>

<td><a href="Hewlett_Packard" class="mw-redirect" title="Hewlett Packard">Hewlett Packard</a>

</td>

<td>100 MHz

</td>

<td>32

</td>

<td>800 nm

</td>

</td>

<td>

</td></tr>

<tr>

<td>1992

</td>

</td>

<td><a href="Cyrix" title="Cyrix">Cyrix</a>

</td>

<td>40 MHz

</td>

<td>16

</td>

<td>

</td>

<td>

</td>

<td>

</td></tr>

<tr>

<td>1993

</td>

<td>HARP-1

</td>

<td><a href="Hitachi" title="Hitachi">Hitachi</a>

</td>

<td>120 MHz

</td>

<td>-

</td>

<td>500 nm

</td>

</td>

<td>

</td></tr>

<tr>

<td>1993

</td>

<td><a href="PowerPC_601" class="mw-redirect" title="PowerPC 601">PowerPC 601</a>

</td>

<td><a href="IBM" title="IBM">IBM</a>, <a href="Motorola" title="Motorola">Motorola</a>

</td>

<td>50–80 MHz

</td>

<td>32

</td>

</td>

<td>2.8

</td>

<td>

</td></tr>

<tr>

<td>1993

</td>

<td><a href="Intel_P5" class="mw-redirect" title="Intel P5">Pentium</a>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>60–66 MHz

</td>

<td>32

</td>

<td>800 nm

</td>

<td>3.1

</td>

<td>

</td></tr>

<tr>

<td>1993

</td>

<td><a href="POWER2" title="POWER2">POWER2</a>

</td>

</td>

<td>55–71.5 MHz

</td>

<td>32

</td>

<td>720 nm

</td>

<td>23

</td>

<td>

</td></tr>

<tr>

<td>1994

</td>

<td><a href="MicroSPARC_II" class="mw-redirect" title="MicroSPARC II">microSPARC II</a>

</td>

<td><a href="Fujitsu" title="Fujitsu">Fujitsu</a>

</td>

<td>60–125 MHz

</td>

<td>-

</td>

<td>500 nm

</td>

<td>2.3

</td>

<td>

</td></tr>

<tr>

<td>1994

</td>

</td>

</td>

<td>-

</td>

<td>32

</td>

<td>-

</td>

<td>

</td>

<td>

</td></tr>

<tr>

<td>1994

</td>

</td>

<td><a href="Motorola" title="Motorola">Motorola</a>

</td>

<td>50 MHz

</td>

<td>32

</td>

<td>600 nm

</td>

<td>2.5

</td>

<td>

</td></tr>

<tr>

<td>1994

</td>

<td><a href="Alpha_21064" title="Alpha 21064">Alpha 21064A</a>

</td>

</td>

<td>200–300 MHz

</td>

<td>64

</td>

<td>500 nm

</td>

<td>2.85

</td>

<td>

</td></tr>

<tr>

<td>1994

</td>

</td>

</td>

<td>100–125 MHz

</td>

<td>64

</td>

<td>650 nm

</td>

<td>2.2

</td>

<td>

</td></tr>

<tr>

<td>1994

</td>

</td>

</td>

<td>75-90 MHz

</td>

<td>64

</td>

<td>700 nm

</td>

<td>3.43

</td>

<td>

</td></tr>

<tr>

<td>1994

</td>

</td>

<td><a href="Hewlett_Packard" class="mw-redirect" title="Hewlett Packard">Hewlett Packard</a>

</td>

<td>125 MHz

</td>

<td>32

</td>

<td>550 nm

</td>

<td>1.26

</td>

<td>

</td></tr>

<tr>

<td>1994

</td>

<td><a href="PowerPC_603" class="mw-redirect" title="PowerPC 603">PowerPC 603</a>

</td>

<td><a href="IBM" title="IBM">IBM</a>, <a href="Motorola" title="Motorola">Motorola</a>

</td>

<td>60–120 MHz

</td>

<td>32

</td>

<td>500 nm

</td>

<td>1.6

</td>

<td>

</td></tr>

<tr>

<td>1994

</td>

<td><a href="PowerPC_604" class="mw-redirect" title="PowerPC 604">PowerPC 604</a>

</td>

<td><a href="IBM" title="IBM">IBM</a>, <a href="Motorola" title="Motorola">Motorola</a>

</td>

<td>100–180 MHz

</td>

<td>32

</td>

<td>500 nm

</td>

<td>3.6

</td>

<td>

</td></tr>

<tr>

<td>1994

</td>

</td>

<td><a href="Hewlett_Packard" class="mw-redirect" title="Hewlett Packard">Hewlett Packard</a>

</td>

<td>100 MHz

</td>

<td>32

</td>

<td>750 nm

</td>

<td>0.90

</td>

<td>

</td></tr>

<tr>

<td>1995

</td>

<td><a href="Alpha_21164" title="Alpha 21164">Alpha 21164</a>

</td>

</td>

<td>266–333 MHz

</td>

<td>64

</td>

<td>500 nm

</td>

<td>9.3

</td>

<td>

</td></tr>

<tr>

<td>1995

</td>

</td>

</td>

<td>-

</td>

<td>32

</td>

<td>-

</td>

<td>

</td>

<td>

</td></tr>

<tr>

<td>1995

</td>

<td><a href="UltraSPARC" title="UltraSPARC">UltraSPARC</a>

</td>

</td>

<td>143–167 MHz

</td>

<td>64

</td>

<td>470 nm

</td>

<td>5.2

</td>

<td>

</td></tr>

<tr>

<td>1995

</td>

<td><a href="HAL_SPARC64" title="HAL SPARC64">SPARC64</a>

</td>

<td><a href="HAL_Computer_Systems" title="HAL Computer Systems">HAL Computer Systems</a>

</td>

<td>101–118 MHz

</td>

<td>64

</td>

<td>400 nm

</td>

<td>-

</td>

<td>

</td></tr>

<tr>

<td>1995

</td>

<td><a href="Pentium_Pro" title="Pentium Pro">Pentium Pro</a>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>150–200 MHz

</td>

<td>32

</td>

</td>

<td>5.5

</td>

<td>

</td></tr>

<tr>

<td>1996

</td>

<td><a href="Alpha_21164" title="Alpha 21164">Alpha 21164A</a>

</td>

</td>

<td>400–500 MHz

</td>

<td>64

</td>

<td>350 nm

</td>

<td>9.7

</td>

<td>

</td></tr>

<tr>

<td>1995

</td>

</td>

</td>

<td>-

</td>

<td>32

</td>

<td>-

</td>

<td>

</td>

<td>

</td></tr>

<tr>

<td>1996

</td>

</td>

</td>

<td>75–100 MHz

</td>

<td>32

</td>

<td>500 nm

</td>

<td>4.3

</td>

<td>

</td></tr>

<tr>

<td>1996

</td>

</td>

</td>

<td>150–250 MHz

</td>

<td>64

</td>

<td>350 nm

</td>

<td>6.7

</td>

<td>

</td></tr>

<tr>

<td>1996

</td>

</td>

</td>

<td>180–250 MHz

</td>

<td>-

</td>

<td>350 nm

</td>

<td>3.7

</td>

<td>

</td></tr>

<tr>

<td>1996

</td>

<td><a href="HAL_SPARC64#SPARC64_II" title="HAL SPARC64">SPARC64 II</a>

</td>

<td><a href="HAL_Computer_Systems" title="HAL Computer Systems">HAL Computer Systems</a>

</td>

<td>141–161 MHz

</td>

<td>64

</td>

<td>350 nm

</td>

<td>-

</td>

<td>

</td></tr>

<tr>

<td>1996

</td>

</td>

<td><a href="Hewlett-Packard" title="Hewlett-Packard">Hewlett-Packard</a>

</td>

<td>160–180 MHz

</td>

<td>64

</td>

<td>500 nm

</td>

<td>3.8

</td>

<td>

</td></tr>

<tr>

<td>1996

</td>

<td><a href="POWER2#POWER2_Super_Chip_(P2SC)" title="POWER2">POWER2 Super Chip (P2SC)</a>

</td>

</td>

<td>150 MHz

</td>

<td>32

</td>

<td>290 nm

</td>

<td>15

</td>

<td>

</td></tr>

<tr>

<td>1997

</td>

</td>

<td><a href="Hitachi" title="Hitachi">Hitachi</a>

</td>

<td>200 MHz

</td>

<td>-

</td>

</td>

</td>

<td>

</td></tr>

<tr>

<td>1997

</td>

</td>

</td>

<td>125 MHz

</td>

<td>64

</td>

<td>? nm

</td>

<td>?

</td>

<td>

</td></tr>

<tr>

<td>1997

</td>

<td><a href="Pentium_II" title="Pentium II">Pentium II</a>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>233–300 MHz

</td>

<td>32

</td>

<td>350 nm

</td>

<td>7.5

</td>

<td>

</td></tr>

<tr>

<td>1997

</td>

<td><a href="PowerPC_620" class="mw-redirect" title="PowerPC 620">PowerPC 620</a>

</td>

<td><a href="IBM" title="IBM">IBM</a>, <a href="Motorola" title="Motorola">Motorola</a>

</td>

<td>120–150 MHz

</td>

<td>64

</td>

<td>350 nm

</td>

<td>6.9

</td>

<td>

</td></tr>

<tr>

<td>1997

</td>

<td><a href="UltraSPARC_II" title="UltraSPARC II">UltraSPARC IIs</a>

</td>

</td>

<td>250–400 MHz

</td>

<td>64

</td>

<td>350 nm

</td>

<td>5.4

</td>

<td>

</td></tr>

<tr>

<td>1997

</td>

</td>

</td>

<td>370 MHz

</td>

<td>32

</td>

<td>500 nm

</td>

<td>7.8

</td>

<td>

</td></tr>

<tr>

<td>1997

</td>

<td><a href="PowerPC_750" class="mw-redirect" title="PowerPC 750">PowerPC 750</a>

</td>

<td><a href="IBM" title="IBM">IBM</a>, <a href="Motorola" title="Motorola">Motorola</a>

</td>

<td>233–366 MHz

</td>

<td>32

</td>

<td>260 nm

</td>

<td>6.35

</td>

<td>

</td></tr>

<tr>

<td>1997

</td>

</td>

</td>

<td>166–233 MHz

</td>

<td>32

</td>

<td>350 nm

</td>

<td>8.8

</td>

<td>

</td></tr>

<tr>

<td>1998

</td>

</td>

</td>

<td>262 MHz

</td>

<td>64

</td>

<td>350 nm

</td>

<td>12.5

</td>

<td>

</td></tr>

<tr>

<td>1998

</td>

<td><a href="Alpha_21264" title="Alpha 21264">Alpha 21264</a>

</td>

</td>

<td>450–600 MHz

</td>

<td>64

</td>

<td>350 nm

</td>

<td>15.2

</td>

<td>

</td></tr>

<tr>

<td>1998

</td>

</td>

</td>

<td>270–400 MHz

</td>

<td>64

</td>

</td>

<td>6.9

</td>

<td>

</td></tr>

<tr>

<td>1998

</td>

<td>RM7000

</td>

</td>

<td>250–300 MHz

</td>

<td>-

</td>

</td>

<td>18

</td>

<td>

</td></tr>

<tr>

<td>1998

</td>

<td><a href="HAL_SPARC64#SPARC64_GP" title="HAL SPARC64">SPARC64 III</a>

</td>

<td><a href="HAL_Computer_Systems" title="HAL Computer Systems">HAL Computer Systems</a>

</td>

<td>250–330 MHz

</td>

<td>64

</td>

<td>240 nm

</td>

<td>17.6

</td>

<td>

</td></tr>

<tr>

<td>1998

</td>

</td>

</td>

<td>500 MHz

</td>

<td>32

</td>

<td>250 nm

</td>

<td>25

</td>

<td>

</td></tr>

<tr>

<td>1998

</td>

</td>

<td><a href="Hewlett_Packard" class="mw-redirect" title="Hewlett Packard">Hewlett Packard</a>

</td>

<td>300–440 MHz

</td>

<td>64

</td>

<td>250 nm

</td>

<td>140

</td>

<td>

</td></tr>

<tr>

<td>1998

</td>

<td><a href="POWER3" title="POWER3">POWER3</a>

</td>

</td>

<td>200 MHz

</td>

<td>64

</td>

<td>250 nm

</td>

<td>15

</td>

<td>

</td></tr>

<tr>

<td>1999

</td>

</td>

</td>

<td>550-637 MHz

</td>

<td>32

</td>

<td>-

</td>

<td>

</td>

<td>

</td></tr>

<tr>

<td>1999

</td>

<td><a href="Emotion_Engine" title="Emotion Engine">Emotion Engine</a>

</td>

<td><a href="Sony" title="Sony">Sony</a>, <a href="Toshiba" title="Toshiba">Toshiba</a>

</td>

<td>294–300 MHz

</td>

<td>-

</td>

</td>

</td>

<td>

</td></tr>

<tr>

<td>1999

</td>

<td><a href="Pentium_III" title="Pentium III">Pentium III</a>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>450–600 MHz

</td>

<td>32

</td>

<td>250 nm

</td>

<td>9.5

</td>

<td>

</td></tr>

<tr>

<td>1999

</td>

</td>

</td>

<td>450 MHz

</td>

<td>64

</td>

<td>220 nm

</td>

<td>34

</td>

<td>2

</td></tr>

<tr>

<td>1999

</td>

<td><a href="PowerPC_7400" class="mw-redirect" title="PowerPC 7400">PowerPC 7400</a>

</td>

<td><a href="Motorola" title="Motorola">Motorola</a>

</td>

<td>350–500 MHz

</td>

<td>32

</td>

</td>

<td>10.5

</td>

<td>

</td></tr>

<tr>

<td>1999

</td>

<td><a href="Athlon" title="Athlon">Athlon</a>

</td>

</td>

<td>500–1000 MHz

</td>

<td>32

</td>

<td>250 nm

</td>

<td>22

</td>

<td>

</td></tr></tbody></table>

<a href="64-bit_computing" title="64-bit computing">64-bit</a> processors became mainstream in the 2000s. Microprocessor clock speeds reached a ceiling because of the <a href="Heat_dissipation" class="mw-redirect" title="Heat dissipation">heat dissipation</a> barrier. Instead of implementing expensive and impractical cooling systems, manufacturers turned to <a href="Parallel_computing" title="Parallel computing">parallel computing</a> in the form of the <a href="Multi-core_processor" title="Multi-core processor">multi-core processor</a>. <a href="Overclocking" title="Overclocking">Overclocking</a> had its roots in the 1990s, but came into its own in the 2000s. Off-the-shelf cooling systems designed for overclocked processors became common, and the <a href="Gaming_computer" title="Gaming computer">gaming PC</a> had its advent as well. Over the decade, transistor counts increased by about an order of magnitude, a trend continued from previous decades. Process sizes decreased about fourfold, from 180 nm to 45 nm.

<th>Date

</th>

<th>Name

</th>

<th>Developer

</th>

<th>Clock

</th>

<th>Process

</th>

<th>Transistors (millions)

</th>

<th><a href="Multicore_processor" class="mw-redirect" title="Multicore processor">Cores per die</a> / <a href="Multi-chip_module" title="Multi-chip module">Dies per module</a>

</th></tr>

<tr>

<td>2000

</td>

<td><a href="Athlon_XP" class="mw-redirect" title="Athlon XP">Athlon XP</a>

</td>

</td>

<td>1.33–1.73 GHz

</td>

<td>180 nm

</td>

<td>37.5

</td>

<td>1 / 1

</td></tr>

<tr>

<td>2000

</td>

<td><a href="Duron" title="Duron">Duron</a>

</td>

</td>

<td>550 MHz–1.3 GHz

</td>

<td>180 nm

</td>

<td>25

</td>

<td>1 / 1

</td></tr>

<tr>

<td>2000

</td>

</td>

</td>

<td>600–750 MHz

</td>

<td>180 nm

</td>

<td>44

</td>

<td>1 / 2

</td></tr>

<tr>

<td>2000

</td>

<td><a href="Pentium_4" title="Pentium 4">Pentium 4</a>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>1.3–2 GHz

</td>

<td>180–130 nm

</td>

<td>42

</td>

<td>1 / 1

</td></tr>

<tr>

<td>2000

</td>

<td>SPARC64 IV

</td>

<td><a href="Fujitsu" title="Fujitsu">Fujitsu</a>

</td>

<td>450–810 MHz

</td>

<td>130 nm

</td>

<td>-

</td>

<td>1 / 1

</td></tr>

<tr>

<td>2000

</td>

</td>

</td>

<td>918 MHz

</td>

<td>180 nm

</td>

<td>47

</td>

<td>1 / 12, 20

</td></tr>

<tr>

<td>2001

</td>

</td>

</td>

<td>500–600 MHz

</td>

<td>130 nm

</td>

<td>7.2

</td>

<td>1 / 1

</td></tr>

<tr>

<td>2001

</td>

<td><a href="POWER4" title="POWER4">POWER4</a>

</td>

</td>

<td>1.1–1.4 GHz

</td>

<td>180–130 nm

</td>

<td>174

</td>

<td>2 / 1, 4

</td></tr>

<tr>

<td>2001

</td>

<td><a href="UltraSPARC_III" title="UltraSPARC III">UltraSPARC III</a>

</td>

</td>

<td>750–1200 MHz

</td>

<td>130 nm

</td>

<td>29

</td>

<td>1 / 1

</td></tr>

<tr>

<td>2001

</td>

<td><a href="Itanium" title="Itanium">Itanium</a>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>733–800 MHz

</td>

<td>180 nm

</td>

<td>25

</td>

<td>1 / 1

</td></tr>

<tr>

<td>2001

</td>

<td><a href="PowerPC_G4#PowerPC_7450_"Voyager"/"V'ger"" title="PowerPC G4">PowerPC 7450</a>

</td>

<td><a href="Motorola" title="Motorola">Motorola</a>

</td>

<td>733–800 MHz

</td>

<td>180–130 nm

</td>

<td>33

</td>

<td>1 / 1

</td></tr>

<tr>

<td>2002

</td>

<td><a href="SPARC64_V" title="SPARC64 V">SPARC64 V</a>

</td>

<td><a href="Fujitsu" title="Fujitsu">Fujitsu</a>

</td>

<td>1.1–1.35 GHz

</td>

<td>130 nm

</td>

<td>190

</td>

<td>1 / 1

</td></tr>

<tr>

<td>2002

</td>

<td><a href="Itanium_2" class="mw-redirect" title="Itanium 2">Itanium 2</a>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>0.9–1 GHz

</td>

<td>180 nm

</td>

<td>410

</td>

<td>1 / 1

</td></tr>

<tr>

<td>2003

</td>

<td><a href="PowerPC_970" title="PowerPC 970">PowerPC 970</a>

</td>

</td>

<td>1.6–2.0 GHz

</td>

<td>130–90 nm

</td>

<td>52

</td>

<td>1 / 1

</td></tr>

<tr>

<td>2003

</td>

<td><a href="Pentium_M" title="Pentium M">Pentium M</a>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>0.9–1.7 GHz

</td>

<td>130–90 nm

</td>

<td>77

</td>

<td>1 / 1

</td></tr>

<tr>

<td>2003

</td>

<td><a href="Opteron" title="Opteron">Opteron</a>

</td>

</td>

<td>1.4–2.4 GHz

</td>

<td>130 nm

</td>

<td>106

</td>

<td>1 / 1

</td></tr>

<tr>

<td>2004

</td>

<td><a href="POWER5" title="POWER5">POWER5</a>

</td>

</td>

<td>1.65–1.9 GHz

</td>

<td>130–90 nm

</td>

<td>276

</td>

<td>2 / 1, 2, 4

</td></tr>

<tr>

<td>2004

</td>

<td><a href="Blue_Gene" class="mw-redirect" title="Blue Gene">PowerPC BGL</a>

</td>

</td>

<td>700 MHz

</td>

<td>130 nm

</td>

<td>95

</td>

<td>2 / 1

</td></tr>

<tr>

<td>2005

</td>

</td>

</td>

<td>

</td>

<td>

</td>

<td>

</td>

<td>

</td></tr>

<tr>

<td>2005

</td>

<td><a href="Opteron" title="Opteron">Opteron "Athens"</a>

</td>

</td>

<td>1.6–3.0 GHz

</td>

<td>90 nm

</td>

<td>114

</td>

<td>1 / 1

</td></tr>

<tr>

<td>2005

</td>

<td><a href="Pentium_D" title="Pentium D">Pentium D</a>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>2.8–3.2 GHz

</td>

<td>90 nm

</td>

<td>115

</td>

<td>1 / 2

</td></tr>

<tr>

<td>2005

</td>

<td><a href="Athlon_64_X2" title="Athlon 64 X2">Athlon 64 X2</a>

</td>

</td>

<td>2–2.4 GHz

</td>

<td>90 nm

</td>

<td>243

</td>

<td>2 / 1

</td></tr>

<tr>

<td>2005

</td>

<td><a href="PowerPC_970" title="PowerPC 970">PowerPC 970MP</a>

</td>

</td>

<td>1.2–2.5 GHz

</td>

<td>90 nm

</td>

<td>183

</td>

<td>2 / 1

</td></tr>

<tr>

<td>2005

</td>

<td><a href="UltraSPARC_IV" title="UltraSPARC IV">UltraSPARC IV</a>

</td>

</td>

<td>1.05–1.35 GHz

</td>

<td>130 nm

</td>

<td>66

</td>

<td>2 / 1

</td></tr>

<tr>

<td>2005

</td>

<td><a href="UltraSPARC_T1" title="UltraSPARC T1">UltraSPARC T1</a>

</td>

</td>

<td>1–1.4 GHz

</td>

<td>90 nm

</td>

<td>300

</td>

<td>8 / 1

</td></tr>

<tr>

<td>2005

</td>

<td><a href="Xenon_(processor)" title="Xenon (processor)">Xenon</a>

</td>

</td>

<td>3.2 GHz

</td>

<td>90–45 nm

</td>

<td>165

</td>

<td>3 / 1

</td></tr>

<tr>

<td>2006

</td>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>1.1–2.33 GHz

</td>

<td>90–65 nm

</td>

<td>151

</td>

<td>2 / 1

</td></tr>

<tr>

<td>2006

</td>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>1.06–2.67 GHz

</td>

<td>65–45 nm

</td>

<td>291

</td>

<td>2 / 1, 2

</td></tr>

<tr>

<td>2006

</td>

</td>

<td><a href="IBM" title="IBM">IBM</a>, <a href="Sony" title="Sony">Sony</a>, <a href="Toshiba" title="Toshiba">Toshiba</a>

</td>

<td>3.2–4.6 GHz

</td>

<td>90–45 nm

</td>

<td>241

</td>

<td>1+8 / 1

</td></tr>

<tr>

<td>2006

</td>

<td><a href="Montecito_(processor)" title="Montecito (processor)">Itanium "Montecito"</a>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>1.4–1.6 GHz

</td>

<td>90 nm

</td>

<td>1720

</td>

<td>2 / 1

</td></tr>

<tr>

<td>2007

</td>

<td><a href="POWER6" title="POWER6">POWER6</a>

</td>

</td>

<td>3.5–4.7 GHz

</td>

<td>65 nm

</td>

<td>790

</td>

<td>2 / 1

</td></tr>

<tr>

<td>2007

</td>

<td><a href="SPARC64_VI" class="mw-redirect" title="SPARC64 VI">SPARC64 VI</a>

</td>

<td><a href="Fujitsu" title="Fujitsu">Fujitsu</a>

</td>

<td>2.15–2.4 GHz

</td>

<td>90 nm

</td>

<td>543

</td>

<td>2 / 1

</td></tr>

<tr>

<td>2007

</td>

<td><a href="UltraSPARC_T2" title="UltraSPARC T2">UltraSPARC T2</a>

</td>

</td>

<td>1–1.4 GHz

</td>

<td>65 nm

</td>

<td>503

</td>

<td>8 / 1

</td></tr>

<tr>

<td>2007

</td>

</td>

<td><a href="Tilera" title="Tilera">Tilera</a>

</td>

<td>600–900 MHz

</td>

<td>90–45 nm

</td>

<td>?

</td>

<td>64 / 1

</td></tr>

<tr>

<td>2007

</td>

<td><a href="Opteron" title="Opteron">Opteron "Barcelona"</a>

</td>

</td>

<td>1.8–3.2 GHz

</td>

<td>65 nm

</td>

<td>463

</td>

<td>4 / 1

</td></tr>

<tr>

<td>2007

</td>

<td><a href="Blue_Gene" class="mw-redirect" title="Blue Gene">PowerPC BGP</a>

</td>

</td>

<td>850 MHz

</td>

<td>90 nm

</td>

<td>208

</td>

<td>4 / 1

</td></tr>

<tr>

<td>2008

</td>

<td><a href="Phenom_(processor)" class="mw-redirect" title="Phenom (processor)">Phenom</a>

</td>

</td>

<td>1.8–2.6 GHz

</td>

<td>65 nm

</td>

<td>450

</td>

<td>2, 3, 4 / 1

</td></tr>

<tr>

<td>2008

</td>

</td>

</td>

<td>4.4 GHz

</td>

<td>65 nm

</td>

<td>993

</td>

<td>4 / 7

</td></tr>

<tr>

<td>2008

</td>

<td><a href="Cell_(microprocessor)" class="mw-redirect" title="Cell (microprocessor)">PowerXCell 8i</a>

</td>

</td>

<td>2.8–4.0 GHz

</td>

<td>65 nm

</td>

<td>250

</td>

<td>1+8 / 1

</td></tr>

<tr>

<td>2008

</td>

<td><a href="SPARC64_VII" class="mw-redirect" title="SPARC64 VII">SPARC64 VII</a>

</td>

<td><a href="Fujitsu" title="Fujitsu">Fujitsu</a>

</td>

<td>2.4–2.88 GHz

</td>

<td>65 nm

</td>

<td>600

</td>

<td>4 / 1

</td></tr>

<tr>

<td>2008

</td>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>0.8–1.6 GHz

</td>

<td>65–45 nm

</td>

<td>47

</td>

<td>1 / 1

</td></tr>

<tr>

<td>2008

</td>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>2.66–3.2 GHz

</td>

<td>45–32 nm

</td>

<td>730

</td>

<td>2, 4, 6 / 1

</td></tr>

<tr>

<td>2008

</td>

<td><a href="TILEPro64" title="TILEPro64">TILEPro64</a>

</td>

<td><a href="Tilera" title="Tilera">Tilera</a>

</td>

<td>600–866 MHz

</td>

<td>90–45 nm

</td>

<td>?

</td>

<td>64 / 1

</td></tr>

<tr>

<td>2008

</td>

<td><a href="Opteron" title="Opteron">Opteron "Shanghai"</a>

</td>

</td>

<td>2.3–2.9 GHz

</td>

<td>45 nm

</td>

<td>751

</td>

<td>4 / 1

</td></tr>

<tr>

<td>2009

</td>

<td><a href="Phenom_II" title="Phenom II">Phenom II</a>

</td>

</td>

<td>2.5–3.2 GHz

</td>

<td>45 nm

</td>

<td>758

</td>

<td>2, 3, 4, 6 / 1

</td></tr>

<tr>

<td>2009

</td>

<td><a href="Opteron" title="Opteron">Opteron "Istanbul"</a>

</td>

</td>

<td>2.2–2.8 GHz

</td>

<td>45 nm

</td>

<td>904

</td>

<td>6 / 1

</td></tr></tbody></table>

A new trend appears, the <a href="Multi-chip_module" title="Multi-chip module">multi-chip module</a> made of several <a href="Chiplet" title="Chiplet">chiplets</a>. This is multiple monolithic chips in a single package. This allows higher integration with several smaller and easier to manufacture chips.

<th>Date

</th>

<th>Name

</th>

<th>Developer

</th>

<th>Clock

</th>

<th>Process

</th>

<th>Transistors (millions)

</th>

<th><a href="Multicore_processor" class="mw-redirect" title="Multicore processor">Cores per die</a> / <a href="Multi-chip_module" title="Multi-chip module">Dies per module</a>

</th>

<th><a href="Multithreading_(computer_hardware)" class="mw-redirect" title="Multithreading (computer hardware)">Threads</a> per core

</th></tr>

<tr>

<td>2010

</td>

<td><a href="POWER7" title="POWER7">POWER7</a>

</td>

</td>

<td>3–4.14 GHz

</td>

<td>45 nm

</td>

<td>1200

</td>

<td>4, 6, 8 / 1, 4

</td>

<td>4

</td></tr>

<tr>

<td>2010

</td>

<td><a href="Tukwila_(processor)" title="Tukwila (processor)">Itanium "Tukwila"</a>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>2 GHz

</td>

<td>65 nm

</td>

<td>2000

</td>

<td>2, 4 / 1

</td>

<td>2

</td></tr>

<tr>

<td>2010

</td>

<td><a href="List_of_AMD_Opteron_microprocessors" class="mw-redirect" title="List of AMD Opteron microprocessors">Opteron "Magny-cours"</a>

</td>

</td>

<td>1.7–2.4 GHz

</td>

<td>45 nm

</td>

<td>1810

</td>

<td>4, 6 / 2

</td>

<td>1

</td></tr>

<tr>

<td>2010

</td>

<td><a href="Beckton_(microprocessor)" class="mw-redirect" title="Beckton (microprocessor)">Xeon "Nehalem-EX"</a>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>1.73–2.66 GHz

</td>

<td>45 nm

</td>

<td>2300

</td>

<td>4, 6, 8 / 1

</td>

<td>2

</td></tr>

<tr>

<td>2010

</td>

</td>

</td>

<td>3.8–5.2 GHz

</td>

<td>45 nm

</td>

<td>1400

</td>

<td>4 / 1, 6

</td>

<td>1

</td></tr>

<tr>

<td>2010

</td>

<td><a href="SPARC_T3" title="SPARC T3">SPARC T3</a>

</td>

</td>

<td>1.6 GHz

</td>

<td>45 nm

</td>

<td>2000

</td>

<td>16 / 1

</td>

<td>8

</td></tr>

<tr>

<td>2010

</td>

<td><a href="SPARC64_VII%2B" class="mw-redirect" title="SPARC64 VII+">SPARC64 VII+</a>

</td>

<td><a href="Fujitsu" title="Fujitsu">Fujitsu</a>

</td>

<td>2.66–3.0 GHz

</td>

<td>45 nm

</td>

<td>?

</td>

<td>4 / 1

</td>

<td>2

</td></tr>

<tr>

<td>2010

</td>

<td><a href="Intel_Nehalem" class="mw-redirect" title="Intel Nehalem">Intel "Westmere"</a>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>1.86–3.33 GHz

</td>

<td>32 nm

</td>

<td>1170

</td>

<td>4–6 / 1

</td>

<td>2

</td></tr>

<tr>

<td>2011

</td>

<td><a href="Intel_Sandy_Bridge" class="mw-redirect" title="Intel Sandy Bridge">Intel "Sandy Bridge"</a>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>1.6–3.4 GHz

</td>

<td>32 nm

</td>

</td>

<td>2, 4 / 1

</td>

<td>(1,) 2

</td></tr>

<tr>

<td>2011

</td>

<td><a href="AMD_Accelerated_Processing_Unit" class="mw-redirect" title="AMD Accelerated Processing Unit">AMD Llano</a>

</td>

</td>

<td>1.0–1.6 GHz

</td>

<td>40 nm

</td>

</td>

<td>1, 2 / 1

</td>

<td>1

</td></tr>

<tr>

<td>2011

</td>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>1.73–2.67 GHz

</td>

<td>32 nm

</td>

<td>2600

</td>

<td>4, 6, 8, 10 / 1

</td>

<td>1–2

</td></tr>

<tr>

<td>2011

</td>

<td><a href="IBM_A2#Blue_Gene.2FQ" title="IBM A2">Power ISA BGQ</a>

</td>

</td>

<td>1.6 GHz

</td>

<td>45 nm

</td>

<td>1470

</td>

<td>18 / 1

</td>

<td>4

</td></tr>

<tr>

<td>2011

</td>

<td><a href="SPARC64_VIIIfx" class="mw-redirect" title="SPARC64 VIIIfx">SPARC64 VIIIfx</a>

</td>

<td><a href="Fujitsu" title="Fujitsu">Fujitsu</a>

</td>

<td>2.0 GHz

</td>

<td>45 nm

</td>

<td>760

</td>

<td>8 / 1

</td>

<td>2

</td></tr>

<tr>

<td>2011

</td>

<td><a href="AMD_Bulldozer" class="mw-redirect" title="AMD Bulldozer">FX "Bulldozer" Interlagos</a>

</td>

</td>

<td>3.1–3.6 GHz

</td>

<td>32 nm

</td>

</td>

<td>4–8 / 2

</td>

<td>1

</td></tr>

<tr>

<td>2011

</td>

<td><a href="SPARC_T4" title="SPARC T4">SPARC T4</a>

</td>

<td><a href="Oracle_Corporation" title="Oracle Corporation">Oracle</a>

</td>

<td>2.8–3 GHz

</td>

<td>40 nm

</td>

<td>855

</td>

<td>8 / 1

</td>

<td>8

</td></tr>

<tr>

<td>2012

</td>

<td><a href="SPARC64_VI" class="mw-redirect" title="SPARC64 VI">SPARC64 IXfx</a>

</td>

<td><a href="Fujitsu" title="Fujitsu">Fujitsu</a>

</td>

<td>1.848 GHz

</td>

<td>40 nm

</td>

<td>1870

</td>

<td>16 / 1

</td>

<td>2

</td></tr>

<tr>

<td>2012

</td>

</td>

</td>

<td>5.5 GHz

</td>

<td>32 nm

</td>

<td>2750

</td>

<td>6 / 6

</td>

<td>1

</td></tr>

<tr>

<td>2012

</td>

<td><a href="POWER7" title="POWER7">POWER7+</a>

</td>

</td>

<td>3.1–5.3 GHz

</td>

<td>32 nm

</td>

<td>2100

</td>

<td>8 / 1, 2

</td>

<td>4

</td></tr>

<tr>

<td>2012

</td>

<td><a href="Poulson_(processor)" class="mw-redirect" title="Poulson (processor)">Itanium "Poulson"</a>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>1.73–2.53 GHz

</td>

<td>32 nm

</td>

<td>3100

</td>

<td>8 / 1

</td>

<td>2

</td></tr>

<tr>

<td>2013

</td>

<td><a href="Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Intel "Haswell"</a>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>1.9–4.4 GHz

</td>

<td>22 nm

</td>

<td>1400

</td>

<td>4 / 1

</td>

<td>2

</td></tr>

<tr>

<td>2013

</td>

<td><a href="SPARC" title="SPARC">SPARC64 X</a>

</td>

<td><a href="Fujitsu" title="Fujitsu">Fujitsu</a>

</td>

<td>2.8–3 GHz

</td>

<td>28 nm

</td>

<td>2950

</td>

<td>16 / 1

</td>

<td>2

</td></tr>

<tr>

<td>2013

</td>

<td><a href="SPARC_T5" title="SPARC T5">SPARC T5</a>

</td>

<td><a href="Oracle_Corporation" title="Oracle Corporation">Oracle</a>

</td>

<td>3.6 GHz

</td>

<td>28 nm

</td>

<td>1500

</td>

<td>16 / 1

</td>

<td>8

</td></tr>

<tr>

<td>2014

</td>

<td><a href="POWER8" title="POWER8">POWER8</a>

</td>

</td>

<td>2.5–5 GHz

</td>

<td>22 nm

</td>

<td>4200

</td>

<td>6, 12 / 1, 2

</td>

<td>8

</td></tr>

<tr>

<td>2014

</td>

<td><a href="Broadwell_(microarchitecture)" title="Broadwell (microarchitecture)">Intel "Broadwell"</a>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>1.8-4 GHz

</td>

<td>14 nm

</td>

<td>1900

</td>

<td>2, 4, 6, 8, 12, 16 / 1, 2, 4

</td>

<td>2

</td></tr>

<tr>

<td>2015

</td>

</td>

</td>

<td>5 GHz

</td>

<td>22 nm

</td>

<td>3990

</td>

<td>8 / 1

</td>

<td>2

</td></tr>

<tr>

<td>2015

</td>

</td>

</td>

<td>3.6 GHz

</td>

<td>28 nm

</td>

<td>2410

</td>

<td>4 / 1

</td>

<td>1

</td></tr>

<tr>

<td>2016

</td>

</td>

<td><a href="SiFive" title="SiFive">SiFive</a>

</td>

<td>320 MHz

</td>

<td>28 nm

</td>

<td>?

</td>

<td>1

</td>

<td>1

</td></tr>

<tr>

<td>2017

</td>

</td>

</td>

<td>3.2–4.1 GHz

</td>

<td>14 nm

</td>

<td>4800

</td>

<td>8, 16 / 1, 2, 4

</td>

<td>2

</td></tr>

<tr>

<td>2017

</td>

</td>

</td>

<td>5.2 GHz

</td>

<td>14 nm

</td>

<td>6100

</td>

<td>10 / 1

</td>

<td>2

</td></tr>

<tr>

<td>2017

</td>

<td><a href="POWER9" title="POWER9">POWER9</a>

</td>

</td>

<td>4 GHz

</td>

<td>14 nm

</td>

<td>8000

</td>

<td>12, 24 / 1

</td>

<td>4, 8

</td></tr>

<tr>

<td>2017

</td>

<td>SPARC M8<a href="#cite_note-SPARC_M8-81">[72]</a>

</td>

<td><a href="Oracle_Corporation" title="Oracle Corporation">Oracle</a>

</td>

<td>5 GHz

</td>

<td>20 nm

</td>

</td>

<td>32

</td>

<td>8

</td></tr>

<tr>

<td>2017

</td>

</td>

<td><a href="SiFive" title="SiFive">SiFive</a>

</td>

<td>1.5 GHz

</td>

<td>28 nm

</td>

<td>250

</td>

<td>4

</td>

<td>1

</td></tr>

<tr>

<td>2018

</td>

<td><a href="Cannon_Lake_(microarchitecture)" class="mw-redirect" title="Cannon Lake (microarchitecture)">Intel "Cannon Lake"</a>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>2.2–3.2 GHz

</td>

<td>10 nm

</td>

<td>?

</td>

<td>2 / 1

</td>

<td>2

</td></tr>

<tr>

<td>2018

</td>

</td>

</td>

<td>2.8–3.7 GHz

</td>

<td>12 nm

</td>

<td>4800

</td>

<td>2, 4, 6, 8 / 1, 2, 4

</td>

<td>1, 2

</td></tr>

<tr>

<td>2018

</td>

</td>

<td><a href="SiFive" title="SiFive">SiFive</a>

</td>

<td>1.5 GHz

</td>

<td>?

</td>

<td>?

</td>

<td>4

</td>

<td>1

</td></tr>

<tr>

<td>2019

</td>

</td>

</td>

<td>2–4.7 GHz

</td>

<td>7 nm, 12nm

</td>

<td>3900

</td>

<td>4, 6, 8 / 1, 2, 4, 6, 8

</td>

<td>2

</td></tr>

<tr>

<td>2019

</td>

</td>

</td>

<td>5.2 GHz

</td>

<td>14 nm

</td>

<td>9200

</td>

<td>12 / 1

</td>

<td>2

</td></tr>

</tbody></table>

<th>Date

</th>

<th>Name

</th>

<th>Developer

</th>

<th>Clock

</th>

<th>Process

</th>

<th>Transistors (millions)

</th>

<th><a href="Multicore_processor" class="mw-redirect" title="Multicore processor">Cores per die</a> / <a href="Multi-chip_module" title="Multi-chip module">Dies per module</a>

</th>

<th><a href="Multithreading_(computer_hardware)" class="mw-redirect" title="Multithreading (computer hardware)">Threads</a> per core

</th></tr>

<tr>

<td>2020

</td>

</td>

</td>

<td>3.4–4.9 GHz

</td>

<td>7 nm, 12nm

</td>

<td>6240–35290

</td>

<td>4, 6, 8 / 1, 2, 4, 8

</td>

<td>2

</td></tr>

<tr>

<td>2020

</td>

<td><a href="Apple_M1" title="Apple M1">M1 Series</a>

</td>

<td>Apple

</td>

<td>3.2 GHz

</td>

<td>5 nm

</td>

<td>16000–144000

</td>

<td>4–8P, 2–4E / 1, 2

</td>

<td>1

</td></tr>

<tr>

<td>2021

</td>

<td><a href="Alder_Lake" title="Alder Lake">Alder Lake</a>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>0.7–5.3 GHz

</td>

<td>7 nm

</td>

<td>?

</td>

<td>0–8P, 2–8E

</td>

<td>1–2

</td></tr>

<tr>

<td>2022

</td>

<td><a href="IBM_Telum_(microprocessor)" class="mw-redirect" title="IBM Telum (microprocessor)">IBM Telum</a>

</td>

<td>IBM

</td>

<td>>5 GHz

</td>

<td>7 nm

</td>

<td>22000

</td>

<td>8

</td>

<td>1

</td></tr>

<tr>

<td>2022

</td>

<td><a href="Apple_M2" title="Apple M2">M2 Series</a>

</td>

<td>Apple

</td>

<td>3.49/2.42 GHz

</td>

<td>5 nm (N5P)

</td>

<td>20000–134000

</td>

<td>4–8P, 4E / 1, 2

</td>

<td>1

</td></tr>

<tr>

<td>2022

</td>

</td>

</td>

<td>2.0–5.7 GHz

</td>

<td>5 nm, 7 nm

</td>

<td>6570

</td>

<td>4, 6, 8 / 1, 2, 4, 8, 12

</td>

<td>2

</td></tr>

<tr>

<td>2023

</td>

</td>

</td>

<td>2.0–3.1 GHz

</td>

<td>5 nm

</td>

<td>8200

</td>

<td>4, 6, 8, 12, 14, 16 / 1, 2, 4, 8

</td>

<td>1, 2

</td></tr>

<tr>

<td>2023

</td>

<td><a href="Apple_M3" title="Apple M3">M3 Series</a>

</td>

<td>Apple

</td>

<td>4.05/2.75 GHz

</td>

<td>3 nm

</td>

<td>25000–92000

</td>

<td>4–12P, 4–6E

</td>

<td>1

</td></tr>

<tr>

<td>2023

</td>

<td><a href="Meteor_Lake" title="Meteor Lake">Meteor Lake</a>

</td>

<td><a href="Intel" title="Intel">Intel</a>

</td>

<td>0.7–5.0 GHz

</td>

<td>5 nm, 7 nm

</td>

<td>?

</td>

<td>2–6P, 4–8E, 2LP-E

</td>

<td>1–2

</td></tr>

<tr>

<td>2024

</td>

<td><a href="Qualcomm_Oryon" class="mw-redirect" title="Qualcomm Oryon">Oryon</a>

</td>

<td><a href="Qualcomm" title="Qualcomm">Qualcomm</a>

</td>

<td>4.3 GHz

</td>

<td>4 nm

</td>

<td>?

</td>

<td>12

</td>

<td>1

</td></tr>

<tr>

<td>2024

</td>

</td>

</td>

<td>4.3 GHz

</td>

<td>5 nm

</td>

<td>8315-20030

</td>

<td>6, 8, 16 / 2, 3

</td>

<td>2

</td></tr></tbody></table>

/* start https://en.wikipedia.org/ */

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<ul><li><a href="Moore's_law" title="Moore's law">Moore's law</a></li>

<li><a href="Transistor_count" title="Transistor count">Transistor count</a> per chip, chronology</li>

<li><a href="Instructions_per_second#Timeline_of_instructions_per_second" title="Instructions per second">Timeline of instructions per second</a> – architectural chip performance chronology</li>

<li><a href="Tick%E2%80%93tock_model" title="Tick–tock model">Tick–tock model</a>, and its successor:

<ul><li><a href="Process%E2%80%93architecture%E2%80%93optimization_model" title="Process–architecture–optimization model">Process–architecture–optimization model</a></li></ul></li></ul>

<div class="mw-heading mw-heading2"><h2 id="References_and_notes">References and notes</h2></div>

<dl><dt>References</dt></dl>

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<dl><dt>Notes</dt></dl>

<ul><li><a rel="nofollow" class="external text" href="http://www.sandpile.org/">sandpile.org</a> for x86 processor information</li>

<li><cite id="CITEREFOgdin1975" class="citation journal cs1">Ogdin, Jerry (January 1975). "Microprocessor scorecard". Euromicro Newsletter. 1 (2): 43–77. <a href="Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1016%2F0303-1268%2875%2990008-5">10.1016/0303-1268(75)90008-5</a>.</cite></li></ul>

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</style><div id="Processor_technologies439" style="font-size:114%;margin:0 4em"><a href="Processor_(computing)" title="Processor (computing)">Processor technologies</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Model_of_computation" title="Model of computation">Models</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Abstract_machine" title="Abstract machine">Abstract machine</a></li>

<li><a href="Stored-program_computer" title="Stored-program computer">Stored-program computer</a></li>

<li><a href="Finite-state_machine" title="Finite-state machine">Finite-state machine</a>

<ul><li><a href="Finite-state_machine_with_datapath" class="mw-redirect" title="Finite-state machine with datapath">with datapath</a></li>

<li><a href="Hierarchical_state_machine" class="mw-redirect" title="Hierarchical state machine">Hierarchical</a></li>

<li><a href="Deterministic_finite_automaton" title="Deterministic finite automaton">Deterministic finite automaton</a></li>

<li><a href="Queue_automaton" title="Queue automaton">Queue automaton</a></li>

<li><a href="Cellular_automaton" title="Cellular automaton">Cellular automaton</a></li>

<li><a href="Quantum_cellular_automaton" title="Quantum cellular automaton">Quantum cellular automaton</a></li></ul></li>

<li><a href="Turing_machine" title="Turing machine">Turing machine</a>

<ul><li><a href="Alternating_Turing_machine" title="Alternating Turing machine">Alternating Turing machine</a></li>

<li><a href="Universal_Turing_machine" title="Universal Turing machine">Universal</a></li>

<li><a href="Post%E2%80%93Turing_machine" title="Post–Turing machine">Post–Turing</a></li>

<li><a href="Quantum_Turing_machine" title="Quantum Turing machine">Quantum</a></li>

<li><a href="Nondeterministic_Turing_machine" title="Nondeterministic Turing machine">Nondeterministic Turing machine</a></li>

<li><a href="Probabilistic_Turing_machine" title="Probabilistic Turing machine">Probabilistic Turing machine</a></li>

<li><a href="Hypercomputation" title="Hypercomputation">Hypercomputation</a></li>

<li><a href="Zeno_machine" title="Zeno machine">Zeno machine</a></li></ul></li>

<li><a href="History_of_general-purpose_CPUs#Belt_machine_architecture" title="History of general-purpose CPUs">Belt machine</a></li>

<li><a href="Stack_machine" title="Stack machine">Stack machine</a></li>

<li><a href="Register_machine" title="Register machine">Register machines</a>

<ul><li><a href="Counter_machine" title="Counter machine">Counter</a></li>

<li><a href="Pointer_machine" title="Pointer machine">Pointer</a></li>

<li><a href="Random-access_machine" title="Random-access machine">Random-access</a></li>

<li><a href="Random-access_stored-program_machine" title="Random-access stored-program machine">Random-access stored program</a></li></ul></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Computer_architecture" title="Computer architecture">Architecture</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Microarchitecture" title="Microarchitecture">Microarchitecture</a></li>

<li><a href="Von_Neumann_architecture" title="Von Neumann architecture">Von Neumann</a></li>

<li><a href="Harvard_architecture" title="Harvard architecture">Harvard</a>

<ul><li><a href="Modified_Harvard_architecture" title="Modified Harvard architecture">modified</a></li></ul></li>

<li><a href="Dataflow_architecture" title="Dataflow architecture">Dataflow</a></li>

<li><a href="Transport_triggered_architecture" title="Transport triggered architecture">Transport-triggered</a></li>

<li><a href="Cellular_architecture" title="Cellular architecture">Cellular</a></li>

<li><a href="Endianness" title="Endianness">Endianness</a></li>

<li><a href="Computer_data_storage" title="Computer data storage">Memory access</a>

<li><a href="Load%E2%80%93store_architecture" title="Load–store architecture">Load–store</a></li>

<li><a href="Register%E2%80%93memory_architecture" title="Register–memory architecture">Register/memory</a></li></ul></li>

<li><a href="Cache_hierarchy" title="Cache hierarchy">Cache hierarchy</a></li>

<li><a href="Memory_hierarchy" title="Memory hierarchy">Memory hierarchy</a>

<ul><li><a href="Virtual_memory" title="Virtual memory">Virtual memory</a></li>

<li><a href="Secondary_storage" class="mw-redirect" title="Secondary storage">Secondary storage</a></li></ul></li>

<li><a href="Heterogeneous_System_Architecture" title="Heterogeneous System Architecture">Heterogeneous</a></li>

<li><a href="Fabric_computing" title="Fabric computing">Fabric</a></li>

<li><a href="Multiprocessing" title="Multiprocessing">Multiprocessing</a></li>

<li><a href="Cognitive_computing" title="Cognitive computing">Cognitive</a></li>

<li><a href="Neuromorphic_engineering" class="mw-redirect" title="Neuromorphic engineering">Neuromorphic</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Instruction_set_architecture" title="Instruction set architecture">Instruction set architectures</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Types</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Orthogonal_instruction_set" title="Orthogonal instruction set">Orthogonal instruction set</a></li>

<li><a href="Application-specific_instruction_set_processor" title="Application-specific instruction set processor">Application-specific</a></li>

<ul><li><a href="TRIPS_architecture" title="TRIPS architecture">TRIPS</a></li></ul></li>

<li><a href="VISC_architecture" title="VISC architecture">VISC architecture</a></li>

<li><a href="Quantum_computing" title="Quantum computing">Quantum computing</a></li>

<li><a href="Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Comparison</a>

<ul><li><a href="Addressing_mode" title="Addressing mode">Addressing modes</a></li></ul></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Instruction sets</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Motorola_68000_series" title="Motorola 68000 series">Motorola 68000 series</a></li>

<li><a href="Stanford_MIPS" title="Stanford MIPS">Stanford MIPS</a></li>

<li>Power

<ul><li><a href="IBM_POWER_architecture" title="IBM POWER architecture">POWER</a></li>

<li><a href="PowerPC" title="PowerPC">PowerPC</a></li>

<li><a href="Power_ISA" title="Power ISA">Power ISA</a></li></ul></li>

<li><a href="Clipper_architecture" title="Clipper architecture">Clipper architecture</a></li>

<li><a href="SPARC" title="SPARC">SPARC</a></li>

<li><a href="SuperH" title="SuperH">SuperH</a></li>

<li><a href="DEC_Alpha" title="DEC Alpha">DEC Alpha</a></li>

<li><a href="ETRAX_CRIS" title="ETRAX CRIS">ETRAX CRIS</a></li>

<li><a href="Unicore" title="Unicore">Unicore</a></li>

<li><a href="IA-64" title="IA-64">Itanium</a></li>

<li><a href="OpenRISC" title="OpenRISC">OpenRISC</a></li>

<li><a href="MicroBlaze" title="MicroBlaze">MicroBlaze</a></li>

<li>System/3x0

<li><a href="Z/Architecture" title="Z/Architecture">z/Architecture</a></li></ul></li>

<li>Tilera ISA</li>

<li><a href="VISC_architecture" title="VISC architecture">VISC architecture</a></li>

<li><a href="Adapteva" class="mw-redirect" title="Adapteva">Epiphany architecture</a></li>

<li><a href="Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Others</a></li></ul>

</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Instruction_cycle" title="Instruction cycle">Execution</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Instruction_pipelining" title="Instruction pipelining">Instruction pipelining</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Pipeline_stall" title="Pipeline stall">Pipeline stall</a></li>

<li><a href="Operand_forwarding" title="Operand forwarding">Operand forwarding</a></li>

<li><a href="Classic_RISC_pipeline" title="Classic RISC pipeline">Classic RISC pipeline</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Hazard_(computer_architecture)" title="Hazard (computer architecture)">Hazards</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Data_dependency" title="Data dependency">Data dependency</a></li>

<li><a href="Structural_hazard" class="mw-redirect" title="Structural hazard">Structural</a></li>

<li><a href="Control_hazard" class="mw-redirect" title="Control hazard">Control</a></li>

<li><a href="False_sharing" title="False sharing">False sharing</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Out-of-order_execution" title="Out-of-order execution">Out-of-order</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Scoreboarding" title="Scoreboarding">Scoreboarding</a></li>

<li><a href="Tomasulo's_algorithm" title="Tomasulo's algorithm">Tomasulo's algorithm</a>

<ul><li><a href="Reservation_station" title="Reservation station">Reservation station</a></li>

<li><a href="Re-order_buffer" title="Re-order buffer">Re-order buffer</a></li></ul></li>

<li><a href="Register_renaming" title="Register renaming">Register renaming</a></li>

<li><a href="Wide-issue" title="Wide-issue">Wide-issue</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Speculative_execution" title="Speculative execution">Speculative</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Branch_predictor" title="Branch predictor">Branch prediction</a></li>

<li><a href="Memory_dependence_prediction" title="Memory dependence prediction">Memory dependence prediction</a></li></ul>

</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Parallel_computing" title="Parallel computing">Parallelism</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Level</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Bit-serial_architecture" title="Bit-serial architecture">Bit-serial</a></li>

<li><a href="Instruction-level_parallelism" title="Instruction-level parallelism">Instruction</a></li>

<li><a href="Instruction_pipelining" title="Instruction pipelining">Pipelining</a>

<ul><li><a href="Scalar_processor" title="Scalar processor">Scalar</a></li>

<li><a href="Superscalar_processor" title="Superscalar processor">Superscalar</a></li></ul></li>

<ul><li><a href="Thread_(computing)" title="Thread (computing)">Thread</a></li>

<li><a href="Process_(computing)" title="Process (computing)">Process</a></li></ul></li>

<ul><li><a href="Vector_processor" title="Vector processor">Vector</a></li></ul></li>

<li><a href="Memory-level_parallelism" title="Memory-level parallelism">Memory</a></li>

<li><a href="Distributed_architecture" class="mw-redirect" title="Distributed architecture">Distributed</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Multithreading_(computer_architecture)" title="Multithreading (computer architecture)">Multithreading</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Temporal_multithreading" title="Temporal multithreading">Temporal</a></li>

<li><a href="Simultaneous_multithreading" title="Simultaneous multithreading">Simultaneous</a>

<ul><li><a href="Hyper-threading" title="Hyper-threading">Hyperthreading</a></li>

<li><a href="Simultaneous_and_heterogeneous_multithreading" title="Simultaneous and heterogeneous multithreading">Simultaneous and heterogenous</a></li></ul></li>

<li><a href="Speculative_multithreading" title="Speculative multithreading">Speculative</a></li>

<li><a href="Preemption_(computing)" title="Preemption (computing)">Preemptive</a></li>

<li><a href="Cooperative_multitasking" title="Cooperative multitasking">Cooperative</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Flynn's_taxonomy" title="Flynn's taxonomy">Flynn's taxonomy</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Single_instruction%2C_multiple_threads" title="Single instruction, multiple threads">Array processing (SIMT)</a></li>

<li><a href="Flynn's_taxonomy#Pipelined_processor" title="Flynn's taxonomy">Pipelined processing</a></li>

<li><a href="Flynn's_taxonomy#Associative_processor" title="Flynn's taxonomy">Associative processing</a></li>

</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Computer_performance" title="Computer performance">Processor performance</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Transistor_count" title="Transistor count">Transistor count</a></li>

<li><a href="Instructions_per_cycle" title="Instructions per cycle">Instructions per cycle</a> (IPC)

<ul><li><a href="Cycles_per_instruction" title="Cycles per instruction">Cycles per instruction</a> (CPI)</li></ul></li>

<li><a href="Instructions_per_second" title="Instructions per second">Instructions per second</a> (IPS)</li>

<li><a href="FLOPS" class="mw-redirect" title="FLOPS">Floating-point operations per second</a> (FLOPS)</li>

<li><a href="Transactions_per_second" title="Transactions per second">Transactions per second</a> (TPS)</li>

<li><a href="SUPS" title="SUPS">Synaptic updates per second</a> (SUPS)</li>

<li><a href="Performance_per_watt" title="Performance per watt">Performance per watt</a> (PPW)</li>

<li><a href="Cache_performance_measurement_and_metric" title="Cache performance measurement and metric">Cache performance metrics</a></li>

<li><a href="Computer_performance_by_orders_of_magnitude" title="Computer performance by orders of magnitude">Computer performance by orders of magnitude</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Processor_(computing)" title="Processor (computing)">Types</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Central_processing_unit" title="Central processing unit">Central processing unit</a> (CPU)</li>

<li><a href="Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a> (GPU)

<ul><li>GPGPU</li></ul></li>

<li><a href="Vector_processor" title="Vector processor">Vector</a></li>

<li><a href="Barrel_processor" title="Barrel processor">Barrel</a></li>

<li><a href="Stream_processing" title="Stream processing">Stream</a></li>

<li><a href="Tile_processor" title="Tile processor">Tile processor</a></li>

<li><a href="Coprocessor" title="Coprocessor">Coprocessor</a></li>

<li><a href="Multi-chip_module" title="Multi-chip module">Multi-chip module</a> (MCM)</li>

<li><a href="System_in_a_package" title="System in a package">System in a package</a> (SiP)</li>

<li><a href="Package_on_a_package" title="Package on a package">Package on a package</a> (PoP)</li></ul>

</div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">By application</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Embedded_system" title="Embedded system">Embedded system</a></li>

<li><a href="Microprocessor" title="Microprocessor">Microprocessor</a></li>

<li><a href="Microcontroller" title="Microcontroller">Microcontroller</a></li>

<li><a href="Mobile_processor" title="Mobile processor">Mobile</a></li>

<li><a href="Ultra-low-voltage_processor" title="Ultra-low-voltage processor">Ultra-low-voltage</a></li>

<li><a href="Soft_microprocessor" title="Soft microprocessor">Soft microprocessor</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Systems on chip</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="System_on_a_chip" title="System on a chip">System on a chip</a> (SoC)</li>

<li><a href="Multiprocessor_system_on_a_chip" class="mw-redirect" title="Multiprocessor system on a chip">Multiprocessor</a> (MPSoC)</li>

<li><a href="Cypress_PSoC" title="Cypress PSoC">Cypress PSoC</a></li>

<li><a href="Network_on_a_chip" title="Network on a chip">Network on a chip</a> (NoC)</li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Hardware_acceleration" title="Hardware acceleration">Hardware accelerators</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Coprocessor" title="Coprocessor">Coprocessor</a></li>

<li><a href="AI_accelerator" class="mw-redirect" title="AI accelerator">AI accelerator</a></li>

<li><a href="Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a> (GPU)</li>

<li><a href="Image_processor" title="Image processor">Image processor</a></li>

<li><a href="Vision_processing_unit" title="Vision processing unit">Vision processing unit</a> (VPU)</li>

<li><a href="Physics_processing_unit" title="Physics processing unit">Physics processing unit</a> (PPU)</li>

<li><a href="Digital_signal_processor" title="Digital signal processor">Digital signal processor</a> (DSP)</li>

<li><a href="Tensor_Processing_Unit" title="Tensor Processing Unit">Tensor Processing Unit</a> (TPU)</li>

<li><a href="Secure_cryptoprocessor" title="Secure cryptoprocessor">Secure cryptoprocessor</a></li>

<li><a href="Network_processor" title="Network processor">Network processor</a></li>

<li><a href="Baseband_processor" title="Baseband processor">Baseband processor</a></li></ul>

</div></td></tr></tbody></table><div>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Word_(computer_architecture)" title="Word (computer architecture)">Word size</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Bit_slicing" title="Bit slicing">bit slicing</a></li>

<li><a href="Word_(computer_architecture)#Table_of_word_sizes" title="Word (computer architecture)">others</a>

<ul><li><a href="Word_(computer_architecture)#Variable-word_architectures" title="Word (computer architecture)">variable</a></li></ul></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Core count</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Single-core" title="Single-core">Single-core</a></li>

<li><a href="Multi-core_processor" title="Multi-core processor">Multi-core</a></li>

<li><a href="Manycore_processor" title="Manycore processor">Manycore</a></li>

<li><a href="Heterogeneous_computing" title="Heterogeneous computing">Heterogeneous architecture</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Components</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Cache_(computing)" title="Cache (computing)">Cache</a>

<ul><li><a href="CPU_cache" title="CPU cache">CPU cache</a></li>

<li><a href="Scratchpad_memory" title="Scratchpad memory">Scratchpad memory</a></li>

<li><a href="Data_cache" class="mw-redirect" title="Data cache">Data cache</a></li>

<li><a href="Instruction_cache" class="mw-redirect" title="Instruction cache">Instruction cache</a></li>

<li><a href="Cache_replacement_policies" title="Cache replacement policies">replacement policies</a></li>

<li><a href="Cache_coherence" title="Cache coherence">coherence</a></li></ul></li>

<li><a href="Clock_rate" title="Clock rate">Clock rate</a></li>

<li><a href="Clock_signal" title="Clock signal">Clock signal</a></li>

</div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Execution_unit" title="Execution unit">Functional units</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Arithmetic_logic_unit" title="Arithmetic logic unit">Arithmetic logic unit</a> (ALU)</li>

<li><a href="Address_generation_unit" title="Address generation unit">Address generation unit</a> (AGU)</li>

<li><a href="Floating-point_unit" title="Floating-point unit">Floating-point unit</a> (FPU)</li>

<li><a href="Memory_management_unit" title="Memory management unit">Memory management unit</a> (MMU)

<ul><li><a href="Load%E2%80%93store_unit" title="Load–store unit">Load–store unit</a></li>

<li><a href="Translation_lookaside_buffer" title="Translation lookaside buffer">Translation lookaside buffer</a> (TLB)</li></ul></li>

<li><a href="Branch_predictor" title="Branch predictor">Branch predictor</a></li>

<li><a href="Branch_target_predictor" title="Branch target predictor">Branch target predictor</a></li>

<li><a href="Memory_controller" title="Memory controller">Integrated memory controller</a> (IMC)

<ul><li><a href="Memory_management_unit" title="Memory management unit">Memory management unit</a></li></ul></li>

<li><a href="Instruction_decoder" class="mw-redirect" title="Instruction decoder">Instruction decoder</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Logic_gate" title="Logic gate">Logic</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Combinational_logic" title="Combinational logic">Combinational</a></li>

<li><a href="Sequential_logic" title="Sequential logic">Sequential</a></li>

<li><a href="Logic_gate" title="Logic gate">Logic gate</a>

<ul><li><a href="Quantum_logic_gate" title="Quantum logic gate">Quantum</a></li>

<li><a href="Gate_array" title="Gate array">Array</a></li></ul></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Hardware_register" title="Hardware register">Registers</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Processor_register" title="Processor register">Processor register</a></li>

<li><a href="Status_register" title="Status register">Status register</a></li>

<li><a href="Stack_register" title="Stack register">Stack register</a></li>

<li><a href="Register_file" title="Register file">Register file</a></li>

<li><a href="Memory_buffer_register" title="Memory buffer register">Memory buffer</a></li>

<li><a href="Memory_address_register" title="Memory address register">Memory address register</a></li>

<li><a href="Program_counter" title="Program counter">Program counter</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Control_unit" title="Control unit">Control unit</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Hardwired_control_unit" class="mw-redirect" title="Hardwired control unit">Hardwired control unit</a></li>

<li><a href="Instruction_unit" title="Instruction unit">Instruction unit</a></li>

<li><a href="Data_buffer" title="Data buffer">Data buffer</a></li>

<li><a href="Write_buffer" title="Write buffer">Write buffer</a></li>

<li><a href="Microcode" title="Microcode">Microcode</a> <a href="ROM_image" title="ROM image">ROM</a></li>

<li><a href="Counter_(digital)" title="Counter (digital)">Counter</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Datapath" title="Datapath">Datapath</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Multiplexer" title="Multiplexer">Multiplexer</a></li>

<li><a href="Demultiplexer" class="mw-redirect" title="Demultiplexer">Demultiplexer</a></li>

<li><a href="Adder_(electronics)" title="Adder (electronics)">Adder</a></li>

<li><a href="Binary_multiplier" title="Binary multiplier">Multiplier</a>

<li><a href="Binary_decoder" title="Binary decoder">Binary decoder</a>

<ul><li><a href="Address_decoder" title="Address decoder">Address decoder</a></li>

<li><a href="Sum-addressed_decoder" title="Sum-addressed decoder">Sum-addressed decoder</a></li></ul></li>

<li><a href="Barrel_shifter" title="Barrel shifter">Barrel shifter</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Electronic_circuit" title="Electronic circuit">Circuitry</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Integrated_circuit" title="Integrated circuit">Integrated circuit</a>

<li><a href="Mixed-signal_integrated_circuit" title="Mixed-signal integrated circuit">Mixed-signal</a></li>

<li><a href="Power_management_integrated_circuit" title="Power management integrated circuit">Power management</a></li></ul></li>

<li><a href="Boolean_circuit" title="Boolean circuit">Boolean</a></li>

<li><a href="Circuit_(computer_science)" title="Circuit (computer science)">Digital</a></li>

<li><a href="Analogue_electronics" title="Analogue electronics">Analog</a></li>

<li><a href="Quantum_circuit" title="Quantum circuit">Quantum</a></li>

<li><a href="Switch#Electronic_switches" title="Switch">Switch</a></li></ul>

</div></td></tr></tbody></table><div>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Power_management" title="Power management">Power management</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Dynamic_frequency_scaling" title="Dynamic frequency scaling">Dynamic frequency scaling</a></li>

<li><a href="Dynamic_voltage_scaling" title="Dynamic voltage scaling">Dynamic voltage scaling</a></li>

<li><a href="Clock_gating" title="Clock gating">Clock gating</a></li>

<li><a href="Performance_per_watt" title="Performance per watt">Performance per watt</a> (PPW)</li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="History_of_general-purpose_CPUs" title="History of general-purpose CPUs">History of general-purpose CPUs</a></li>

<li><a href="Processor_design" title="Processor design">Processor design</a></li>

<li><a href="Digital_electronics" title="Digital electronics">Digital electronics</a></li>

<li><a href="Hardware_security_module" title="Hardware security module">Hardware security module</a></li>

<li><a href="Semiconductor_device_fabrication" title="Semiconductor device fabrication">Semiconductor device fabrication</a></li>

<li><a href="Tick%E2%80%93tock_model" title="Tick–tock model">Tick–tock model</a></li>

<li><a href="Pin_grid_array" title="Pin grid array">Pin grid array</a></li>

<li><a href="Chip_carrier" title="Chip carrier">Chip carrier</a></li></ul>

</div></td></tr></tbody></table></div></div><div><div class="zim-footer">

This article is issued from <a class="external text" title="Last edited on 2025-08-06" href="https://en.wikipedia.org/wiki/?title=Microprocessor_chronology&oldid=1304463234">Wikipedia</a>. The text is available under <a class="external text" href="https://creativecommons.org/licenses/by-sa/4.0/deed.en">Creative Commons Attribution-Share Alike 4.0</a> unless otherwise noted. Additional terms may apply for the media files.

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